correct_err.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    09:54:30 04/14/08
-- Design Name:    
-- Module Name:    correct_err - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity correct_err is
	port
	(
	  clk:in std_logic;
	  reset: in std_logic;
	  en_all:in std_logic;
	  data_org:in std_logic_vector(7 downto 0);
	  sum1:in std_logic_vector(12 downto 0);
	  sum2:in std_logic_vector(12 downto 0);
	  sum3:in std_logic_vector(12 downto 0);
	  sum4:in std_logic_vector(12 downto 0);
	  sum5:in std_logic_vector(12 downto 0);
	  sum6:in std_logic_vector(12 downto 0);
	  sum7:in std_logic_vector(12 downto 0);
	  sum8:in std_logic_vector(12 downto 0);
	  data_m:out std_logic_vector(7 downto 0)				---msb_lsb---
	);
end correct_err;

architecture Behavioral of correct_err is

begin
		process(clk,reset)
			begin
				if(reset='1')then
					data_m(7)<='0';
				elsif(clk'event and clk='1')then
					if(en_all='1')then
						if sum1="0000000000000" then
							data_m(7)<=not data_org(7);
						else
							data_m(7)<=data_org(7);
						end if;
					end if;
				end if;
		end process;

		process(clk,reset)
			begin
				if(reset='1')then
					data_m(6)<='0';
				elsif(clk'event and clk='1')then
					if(en_all='1')then
						if sum2="0000000000000" then
							data_m(6)<=not data_org(6);
						else
							data_m(6)<=data_org(6);
						end if;
					end if;
				end if;
		end process;

		process(clk,reset)
			begin
				if(reset='1')then
					data_m(5)<='0';
				elsif(clk'event and clk='1')then
					if(en_all='1')then
							if sum3="0000000000000" then
								data_m(5)<=not data_org(5);
							else
								data_m(5)<=data_org(5);
							end if;
					end if;
				end if;
		end process;

		process(clk,reset)
			begin
				if(reset='1')then
					data_m(4)<='0';
				elsif(clk'event and clk='1')then
					if(en_all='1')then
						if sum4="0000000000000" then
							data_m(4)<=not data_org(4);
						else
							data_m(4)<=data_org(4);
						end if;
					end if;
				end if;
		end process;

		process(clk,reset)
			begin
				if(reset='1')then
					data_m(3)<='0';
				elsif(clk'event and clk='1')then
					if(en_all='1')then
						if sum5="0000000000000" then
							data_m(3)<=not data_org(3);
						else
							data_m(3)<=data_org(3);
						end if;
					end if;
				end if;
		end process;

		process(clk,reset)
			begin
				if(reset='1')then
					data_m(2)<='0';
				elsif(clk'event and clk='1')then
					if(en_all='1')then
						if sum6="0000000000000" then
							data_m(2)<=not data_org(2);
						else
							data_m(2)<=data_org(2);
						end if;
					end if;
				end if;
		end process;

		process(clk,reset)
			begin
				if(reset='1')then
					data_m(1)<='0';
				elsif(clk'event and clk='1')then
					if(en_all='1')then
						if sum7="0000000000000" then
							data_m(1)<=not data_org(1);
						else
							data_m(1)<=data_org(1);
						end if;
					end if;
				end if;
		end process;

		process(clk,reset)
			begin
				if(reset='1')then
					data_m(0)<='0';
				elsif(clk'event and clk='1')then
					if(en_all='1')then
						if sum8="0000000000000" then
							data_m(0)<=not data_org(0);
						else
							data_m(0)<=data_org(0);
						end if;
					end if;
				end if;
		end process;
					

end Behavioral;