tb_bch_decoder.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:   10:46:01 05/01/2008
-- Design Name:   bch_decoder
-- Module Name:   tb_bch_decoder.vhd
-- Project Name:  BCH_decoder
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: bch_decoder
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_textio.all;
use	std.textio.all;

ENTITY tb_bch_decoder_vhd IS
END tb_bch_decoder_vhd;

ARCHITECTURE behavior OF tb_bch_decoder_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT bch_decoder
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;
		din : IN std_logic_vector(7 downto 0);
		en_in : IN std_logic;
		out_en:out std_logic;          
		dout : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL en_in :  std_logic := '0';
	SIGNAL din :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL dout :  std_logic_vector(7 downto 0);
	signal out_en:std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: bch_decoder PORT MAP(
		clk => clk,
		reset => reset,
		din => din,
		en_in => en_in,
		 out_en=>out_en,
		dout => dout
	);

clk_pro:
	process
		begin
		clk<='1';
		wait for 50ns;
		clk<='0';
		wait for 50ns;
	end process;

reset_pro:
	process
		begin
			reset<='1';
			wait for 700ns;
			reset<='0';
			wait;
	end process;

process
	begin
		en_in<='0';
		wait for 700ns;
		en_in<='1';
		wait for 5120000ns;
		en_in<='0';
		wait;
end process;



process(reset,clk)		---- read data from file
        file infile: TEXT open read_mode is "word.txt";
        variable l: LINE;
        variable varin: std_logic_vector(7 downto 0);
	begin
        if (reset='1') then
			DIN <= (others=>'0');
        elsif ((clk'event) and (clk='0')) then
            if(endfile(infile)) then
	            file_close(infile);
				      file_open(infile, "word.txt", read_mode);
			      end if;
			
            readline(infile,l);
            read (l,varin);
            DIN <= varin;
        end if;
    end process;



END;