sp.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    15:28:05 04/26/08
-- Design Name:    
-- Module Name:    sp - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sp is
	port
		(
			clk:in std_logic;
			reset:in std_logic;
			en_all:in std_logic;
			en_init:in std_logic;
			v:in std_logic_vector(12 downto 0);
			v1:out std_logic_vector(12 downto 0);
			v2:out std_logic_vector(12 downto 0);
			v3:out std_logic_vector(12 downto 0);
			v4:out std_logic_vector(12 downto 0);
			v5:out std_logic_vector(12 downto 0);
			v6:out std_logic_vector(12 downto 0);
			v7:out std_logic_vector(12 downto 0);
			v8:out std_logic_vector(12 downto 0);
			v9:out std_logic_vector(12 downto 0);
			v10:out std_logic_vector(12 downto 0);
			v11:out std_logic_vector(12 downto 0)
			);
end sp;

architecture Behavioral of sp is

signal cnt:integer range 15 downto 0;

signal v1_tmp:std_logic_vector(12 downto 0);
signal v2_tmp:std_logic_vector(12 downto 0);
signal v3_tmp:std_logic_vector(12 downto 0);
signal v4_tmp:std_logic_vector(12 downto 0);
signal v5_tmp:std_logic_vector(12 downto 0);
signal v6_tmp:std_logic_vector(12 downto 0);
signal v7_tmp:std_logic_vector(12 downto 0);
signal v8_tmp:std_logic_vector(12 downto 0);
signal v9_tmp:std_logic_vector(12 downto 0);
signal v10_tmp:std_logic_vector(12 downto 0);
signal v11_tmp:std_logic_vector(12 downto 0);

begin
	process(clk,reset)
		begin
		if(reset='1')then
			v1<=(others=>'0');
		   v2<=(others=>'0');
			v3<=(others=>'0');
			v4<=(others=>'0');
			v5<=(others=>'0');
			v6<=(others=>'0');
			v7<=(others=>'0');
			v8<=(others=>'0');
			v9<=(others=>'0');
			v10<=(others=>'0');
			v11<=(others=>'0');
			v1_tmp<=(others=>'0');
			v2_tmp<=(others=>'0');
			v3_tmp<=(others=>'0');
			v4_tmp<=(others=>'0');
			v5_tmp<=(others=>'0');
			v6_tmp<=(others=>'0');
			v7_tmp<=(others=>'0');
			v8_tmp<=(others=>'0');
			v9_tmp<=(others=>'0');
			v10_tmp<=(others=>'0');
			v11_tmp<=(others=>'0');
			cnt<=0;
		 elsif(clk'event and clk='1')then
				if en_init='1'then
						cnt<=0;
			 	elsif en_all='1'then
					if cnt=11 then
						cnt<=1;			  ---------------
					else	
						cnt<=cnt+1;
					end if;
			 	 case cnt is
			  		when 1=>v11_tmp<=v;
					when 2=>v10_tmp<=v;
					when 3=>v9_tmp<=v;
					when 4=>v8_tmp<=v;
					when 5=>v7_tmp<=v;
					when 6=>v6_tmp<=v;
					when 7=>v5_tmp<=v;
					when 8=>v4_tmp<=v;
					when 9=>v3_tmp<=v;
					when 10=>v2_tmp<=v;
					when others=>v1_tmp<=v;
				 end case;
			  end if;
			  					v1<=v1_tmp;
								v2<=v2_tmp;
								v3<=v3_tmp;
								v4<=v4_tmp;
								v5<=v5_tmp;
								v6<=v6_tmp;
								v7<=v7_tmp;
								v8<=v8_tmp;
								v9<=v9_tmp;
								v10<=v10_tmp;
								v11<=v11_tmp;
		 end if;
end process;
end Behavioral;