data_map.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    16:55:14 05/04/08
-- Design Name:    
-- Module Name:    data_map - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
															  ---------------1->1,0->-1
entity data_map is
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_in:in std_logic;
	data_in:in std_logic_vector(7 downto 0);
	en_out:out std_logic;
	data_out0:out std_logic_vector(15 downto 0);	
	data_out1:out std_logic_vector(15 downto 0);
	data_out2:out std_logic_vector(15 downto 0);
	data_out3:out std_logic_vector(15 downto 0);
	data_out4:out std_logic_vector(15 downto 0);
	data_out5:out std_logic_vector(15 downto 0);
	data_out6:out std_logic_vector(15 downto 0);
	data_out7:out std_logic_vector(15 downto 0)
	);
end data_map;

architecture Behavioral of data_map is

begin
	process(clk,reset)
		begin
			if(reset='1')then
				en_out<='0';
			elsif(clk'event and clk='1')then
				en_out<=en_in;
			end if;
	end process;
		
	process(clk,reset)
		begin
			if(reset='1')then
				data_out0<=(others=>'0');
			elsif(clk'event and clk='1')then
				if (data_in(0)='1')then
					data_out0<="0000100000000000";
				else
					data_out0<="1111100000000000"; 
				end if;
			end if;
	end process;				

	process(clk,reset)
		begin
			if(reset='1')then
				data_out1<=(others=>'0');
			elsif(clk'event and clk='1')then
				if (data_in(1)='1')then
					data_out1<="0000100000000000";
				else
					data_out1<="1111100000000000"; 
				end if;
			end if;
	end process;

	process(clk,reset)
		begin
			if(reset='1')then
				data_out2<=(others=>'0');
			elsif(clk'event and clk='1')then
				if (data_in(2)='1')then
					data_out2<="0000100000000000";
				else
					data_out2<="1111100000000000"; 
				end if;
			end if;
	end process;
	
	process(clk,reset)
		begin
			if(reset='1')then
				data_out3<=(others=>'0');
			elsif(clk'event and clk='1')then
				if (data_in(3)='1')then
					data_out3<="0000100000000000";
				else
					data_out3<="1111100000000000"; 
				end if;
			end if;
	end process;

	process(clk,reset)
		begin
			if(reset='1')then
				data_out4<=(others=>'0');
			elsif(clk'event and clk='1')then
				if (data_in(4)='1')then
					data_out4<="0000100000000000";
				else
					data_out4<="1111100000000000"; 
				end if;
			end if;
	end process;

	process(clk,reset)
		begin
			if(reset='1')then
				data_out5<=(others=>'0');
			elsif(clk'event and clk='1')then
				if (data_in(5)='1')then
					data_out5<="0000100000000000";
				else
					data_out5<="1111100000000000"; 
				end if;
			end if;
	end process;

	process(clk,reset)
		begin
			if(reset='1')then
				data_out6<=(others=>'0');
			elsif(clk'event and clk='1')then
				if (data_in(6)='1')then
					data_out6<="0000100000000000";
				else
					data_out6<="1111100000000000"; 
				end if;
			end if;
	end process;																		

	process(clk,reset)
		begin
			if(reset='1')then
				data_out7<=(others=>'0');
			elsif(clk'event and clk='1')then
				if (data_in(7)='1')then
					data_out7<="0000100000000000";
				else
					data_out7<="1111100000000000"; 
				end if;
			end if;
	end process;
				
end Behavioral;