chien3.vhd

bch 编码和译码

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    21:33:14 04/09/08
-- Design Name:    
-- Module Name:    chien3 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity chien3 is
port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		err_pol:in std_logic_vector(12 downto 0);
		product1:out std_logic_vector(12 downto 0);
		product2:out std_logic_vector(12 downto 0);
		product3:out std_logic_vector(12 downto 0);
		product4:out std_logic_vector(12 downto 0);
		product5:out std_logic_vector(12 downto 0);
		product6:out std_logic_vector(12 downto 0);
		product7:out std_logic_vector(12 downto 0);
		product8:out std_logic_vector(12 downto 0)
	 );
end chien3;

architecture Behavioral of chien3 is

component mul3
	port(
		mul3_in:in std_logic_vector(12 downto 0);
		mul3_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul6
	port(
		mul6_in:in std_logic_vector(12 downto 0);
		mul6_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul9
	port(
		mul9_in:in std_logic_vector(12 downto 0);
		mul9_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul12
	port(
		mul12_in:in std_logic_vector(12 downto 0);
		mul12_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul15
	port(
		mul15_in:in std_logic_vector(12 downto 0);
		mul15_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul18
	port(
		mul18_in:in std_logic_vector(12 downto 0);
		mul18_out:out std_logic_vector(12 downto 0)
		);
end component;
component mul21
	port(
		mul21_in:in std_logic_vector(12 downto 0);
		mul21_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul24
	port(
		mul24_in:in std_logic_vector(12 downto 0);
		mul24_out:out std_logic_vector(12 downto 0)
		);
end component;

component mul4112
	port(
		mul4112_in:in std_logic_vector(12 downto 0);
		mul4112_out:out std_logic_vector(12 downto 0)
		);
end component;

signal d:std_logic_vector(12 downto 0);
signal product1_tmp:std_logic_vector(12 downto 0);
signal product2_tmp:std_logic_vector(12 downto 0);
signal product3_tmp:std_logic_vector(12 downto 0);
signal product4_tmp:std_logic_vector(12 downto 0);
signal product5_tmp:std_logic_vector(12 downto 0);
signal product6_tmp:std_logic_vector(12 downto 0);
signal product7_tmp:std_logic_vector(12 downto 0);
signal product8_tmp:std_logic_vector(12 downto 0);
signal sel_tmp:std_logic_vector(12 downto 0);
signal err_pol_m:std_logic_vector(12 downto 0);
--signal cnt:integer range 1000 downto 0;
--signal en_sel: std_logic;
begin

d_pro:
	process(clk,reset)
		begin
			if(reset='1')then
				d<=(others=>'0');
			elsif(clk'event and clk='1')then
				if(en_all='1')then
					d<=product8_tmp;
				end if;
			end if;
	end process;

mul4112_pro:
		mul4112
			port map
			(
			mul4112_in=>err_pol,
			mul4112_out=>err_pol_m
			);			

sel_pro:
	process(clk)
		begin
			if(en_all='1')then
				if(en_sel='0')then
					sel_tmp<=d;
				else
					sel_tmp<=err_pol_m;
				end if;
			end if;
	end process;

mul3_pro:
	mul3
	port map
	(
	mul3_in=>sel_tmp,
	mul3_out=>product1_tmp
	);

mul6_pro:
	mul6
	port map
	(
	mul6_in=>sel_tmp,
	mul6_out=>product2_tmp
	);

mul9_pro:
	mul9
	port map
	(
	mul9_in=>sel_tmp,
	mul9_out=>product3_tmp
	);

mul12_pro:
	mul12
	port map
	(
	mul12_in=>sel_tmp,
	mul12_out=>product4_tmp
	);

mul15_pro:
	mul15
	port map
	(
	mul15_in=>sel_tmp,
	mul15_out=>product5_tmp
	);

mul18_pro:
	mul18
	port map
	(
	mul18_in=>sel_tmp,
	mul18_out=>product6_tmp
	);

mul21_pro:
	mul21
	port map
	(
	mul21_in=>sel_tmp,
	mul21_out=>product7_tmp
	);	

mul24_pro:
	mul24
	port map
	(
	mul24_in=>sel_tmp,
	mul24_out=>product8_tmp
	);

product1<=product1_tmp;
product2<=product2_tmp;
product3<=product3_tmp;
product4<=product4_tmp;
product5<=product5_tmp;	
product6<=product6_tmp;
product7<=product7_tmp;
product8<=product8_tmp;

--cnt_pro:
--	process(clk,reset)
--		begin
--			if(reset='1')then
--				cnt<=0;
--			elsif(clk'event and clk='1')then
--				if(en_all='1')then
--					if cnt=511 then  -- *
--						cnt<=0;			 --*
--					else
--						cnt<=cnt+1;
--					end if;
--				end if;
--			end if;
--	end process;
--
--
--sel_proc:
--	process(clk)
--		begin
--			if(clk'event and clk='1')then
--				if cnt=0 then			  ---*---
--					en_sel<='1';
--				else
--					en_sel<='0';
--				end if;
--			end if;
--	end process;
													 
end Behavioral;