eucild_m.vhd

bch 编码和译码

	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell16
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell17
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell18
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell19
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell20
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

signal deg_ro1:integer range 63 downto -63;
signal deg_qo1:integer range 63 downto -63;
signal ro1:std_logic_vector(12 downto 0);
signal qo1:std_logic_vector(12 downto 0);
signal vo1:std_logic_vector(12 downto 0);
signal uo1:std_logic_vector(12 downto 0);
signal start_o1:std_logic;
signal stop_o1:std_logic;

signal deg_ro2:integer range 63 downto -63;
signal deg_qo2:integer range 63 downto -63;
signal ro2:std_logic_vector(12 downto 0);
signal qo2:std_logic_vector(12 downto 0);
signal vo2:std_logic_vector(12 downto 0);
signal uo2:std_logic_vector(12 downto 0);
signal start_o2:std_logic;
signal stop_o2:std_logic;
  
signal deg_ro3:integer range 63 downto -63;
signal deg_qo3:integer range 63 downto -63;
signal ro3:std_logic_vector(12 downto 0);
signal qo3:std_logic_vector(12 downto 0);
signal vo3:std_logic_vector(12 downto 0);
signal uo3:std_logic_vector(12 downto 0);
signal start_o3:std_logic;
signal stop_o3:std_logic;
  
signal deg_ro4:integer range 63 downto -63;
signal deg_qo4:integer range 63 downto -63;
signal ro4:std_logic_vector(12 downto 0);
signal qo4:std_logic_vector(12 downto 0);
signal vo4:std_logic_vector(12 downto 0);
signal uo4:std_logic_vector(12 downto 0);
signal start_o4:std_logic;
signal stop_o4:std_logic;
  
signal deg_ro5:integer range 63 downto -63;
signal deg_qo5:integer range 63 downto -63;
signal ro5:std_logic_vector(12 downto 0);
signal qo5:std_logic_vector(12 downto 0);
signal vo5:std_logic_vector(12 downto 0);
signal uo5:std_logic_vector(12 downto 0);
signal start_o5:std_logic;
signal stop_o5:std_logic;
  
signal deg_ro6:integer range 63 downto -63;
signal deg_qo6:integer range 63 downto -63;
signal ro6:std_logic_vector(12 downto 0);
signal qo6:std_logic_vector(12 downto 0);
signal vo6:std_logic_vector(12 downto 0);
signal uo6:std_logic_vector(12 downto 0);
signal start_o6:std_logic;
signal stop_o6:std_logic;
  
signal deg_ro7:integer range 63 downto -63;
signal deg_qo7:integer range 63 downto -63;
signal ro7:std_logic_vector(12 downto 0);
signal qo7:std_logic_vector(12 downto 0);
signal vo7:std_logic_vector(12 downto 0);
signal uo7:std_logic_vector(12 downto 0);
signal start_o7:std_logic;
signal stop_o7:std_logic;
  
signal deg_ro8:integer range 63 downto -63;
signal deg_qo8:integer range 63 downto -63;
signal ro8:std_logic_vector(12 downto 0);
signal qo8:std_logic_vector(12 downto 0);
signal vo8:std_logic_vector(12 downto 0);
signal uo8:std_logic_vector(12 downto 0);
signal start_o8:std_logic;
signal stop_o8:std_logic;
  
signal deg_ro9:integer range 63 downto -63;
signal deg_qo9:integer range 63 downto -63;
signal ro9:std_logic_vector(12 downto 0);
signal qo9:std_logic_vector(12 downto 0);
signal vo9:std_logic_vector(12 downto 0);
signal uo9:std_logic_vector(12 downto 0);
signal start_o9:std_logic;
signal stop_o9:std_logic;
  
signal deg_ro10:integer range 63 downto -63;
signal deg_qo10:integer range 63 downto -63;
signal ro10:std_logic_vector(12 downto 0);
signal qo10:std_logic_vector(12 downto 0);
signal vo10:std_logic_vector(12 downto 0);
signal uo10:std_logic_vector(12 downto 0);
signal start_o10:std_logic;
signal stop_o10:std_logic;
  
signal deg_ro11:integer range 63 downto -63;
signal deg_qo11:integer range 63 downto -63;
signal ro11:std_logic_vector(12 downto 0);
signal qo11:std_logic_vector(12 downto 0);
signal vo11:std_logic_vector(12 downto 0);
signal uo11:std_logic_vector(12 downto 0);
signal start_o11:std_logic;
signal stop_o11:std_logic;
  
signal deg_ro12:integer range 63 downto -63;
signal deg_qo12:integer range 63 downto -63;
signal ro12:std_logic_vector(12 downto 0);
signal qo12:std_logic_vector(12 downto 0);
signal vo12:std_logic_vector(12 downto 0);
signal uo12:std_logic_vector(12 downto 0);
signal start_o12:std_logic;
signal stop_o12:std_logic;
  
signal deg_ro13:integer range 63 downto -63;
signal deg_qo13:integer range 63 downto -63;
signal ro13:std_logic_vector(12 downto 0);
signal qo13:std_logic_vector(12 downto 0);
signal vo13:std_logic_vector(12 downto 0);
signal uo13:std_logic_vector(12 downto 0);
signal start_o13:std_logic;
signal stop_o13:std_logic;
  
signal deg_ro14:integer range 63 downto -63;
signal deg_qo14:integer range 63 downto -63;
signal ro14:std_logic_vector(12 downto 0);
signal qo14:std_logic_vector(12 downto 0);
signal vo14:std_logic_vector(12 downto 0);
signal uo14:std_logic_vector(12 downto 0);
signal start_o14:std_logic;
signal stop_o14:std_logic;
  
signal deg_ro15:integer range 63 downto -63;
signal deg_qo15:integer range 63 downto -63;
signal ro15:std_logic_vector(12 downto 0);
signal qo15:std_logic_vector(12 downto 0);
signal vo15:std_logic_vector(12 downto 0);
signal uo15:std_logic_vector(12 downto 0);
signal start_o15:std_logic;
signal stop_o15:std_logic;
  
signal deg_ro16:integer range 63 downto -63;
signal deg_qo16:integer range 63 downto -63;
signal ro16:std_logic_vector(12 downto 0);
signal qo16:std_logic_vector(12 downto 0);
signal vo16:std_logic_vector(12 downto 0);
signal uo16:std_logic_vector(12 downto 0);
signal start_o16:std_logic;
signal stop_o16:std_logic;
  
signal deg_ro17:integer range 63 downto -63;
signal deg_qo17:integer range 63 downto -63;
signal ro17:std_logic_vector(12 downto 0);
signal qo17:std_logic_vector(12 downto 0);
signal vo17:std_logic_vector(12 downto 0);
signal uo17:std_logic_vector(12 downto 0);
signal start_o17:std_logic;
signal stop_o17:std_logic;
  
signal deg_ro18:integer range 63 downto -63;
signal deg_qo18:integer range 63 downto -63;
signal ro18:std_logic_vector(12 downto 0);
signal qo18:std_logic_vector(12 downto 0);
signal vo18:std_logic_vector(12 downto 0);
signal uo18:std_logic_vector(12 downto 0);
signal start_o18:std_logic;
signal stop_o18:std_logic;
  
signal deg_ro19:integer range 63 downto -63;
signal deg_qo19:integer range 63 downto -63;
signal ro19:std_logic_vector(12 downto 0);
signal qo19:std_logic_vector(12 downto 0);
signal vo19:std_logic_vector(12 downto 0);
signal uo19:std_logic_vector(12 downto 0);
signal start_o19:std_logic;
signal stop_o19:std_logic;
  
signal deg_ro20:integer range 63 downto -63;
signal deg_qo20:integer range 63 downto -63;
signal ro20:std_logic_vector(12 downto 0);
signal qo20:std_logic_vector(12 downto 0);
signal vo20:std_logic_vector(12 downto 0);
signal uo20:std_logic_vector(12 downto 0);
signal start_o20:std_logic;
signal stop_o20:std_logic;

signal stop_i1:std_logic;
signal stop_i2:std_logic;
signal stop_i3:std_logic;
signal stop_i4:std_logic;
signal stop_i5:std_logic;
signal stop_i6:std_logic;
signal stop_i7:std_logic;
signal stop_i8:std_logic;
signal stop_i9:std_logic;
signal stop_i10:std_logic;
signal stop_i11:std_logic;
signal stop_i12:std_logic;
signal stop_i13:std_logic;
signal stop_i14:std_logic;
signal stop_i15:std_logic;
signal stop_i16:std_logic;
signal stop_i17:std_logic;
signal stop_i18:std_logic;
signal stop_i19:std_logic;
signal stop_i20:std_logic;

signal sel:std_logic;
signal u_tmp:std_logic_vector(12 downto 0);
signal stop_o_tmp:std_logic;

begin

cell1_pro:
	cell1
		port map
		(
		clk=>clk,
		reset=>reset,
		en_all=>en_all,
		en_init=>en_init,
		deg_r=>deg_r,
		deg_q=>deg_q,
		r=>r,
		q=>q,
		v=>v,
		u=>u,
		start=>start,
		stop_i=>stop_o1,
		deg_ro=>deg_ro1,
		deg_qo=>deg_qo1,
		ro=>ro1,
		qo=>qo1,
		vo=>vo1,
		uo=>uo1,
		start_o=>start_o1,
		stop_o=>stop_i1
		);

cell2_pro:
   cell2
      port map
      (
      clk=>clk,
      reset=>reset,
      en_all=>en_all,
		en_init=>en_init,
      deg_r=>deg_ro1,
      deg_q=>deg_qo1,
      r=>ro1,
      q=>qo1,
      v=>vo1,
      u=>uo1,
      start=>start_o1,
      stop_i=>stop_o2,
      deg_ro=>deg_ro2,
      deg_qo=>deg_qo2,
      ro=>ro2,
      qo=>qo2,
      vo=>vo2,
      uo=>uo2,
      start_o=>start_o2,
      stop_o=>stop_i2 
      );
      
cell3_pro:
   cell3
      port map
      (
      clk=>clk,
      reset=>reset,
      en_all=>en_all,
		en_init=>en_init,
      deg_r=>deg_ro2,
      deg_q=>deg_qo2,
      r=>ro2,
      q=>qo2,
      v=>vo2,
      u=>uo2,
      start=>start_o2,
      stop_i=>stop_o3,
      deg_ro=>deg_ro3,
      deg_qo=>deg_qo3,
      ro=>ro3,
      qo=>qo3,
      vo=>vo3,
      uo=>uo3,
      start_o=>start_o3,
      stop_o=>stop_i3 
      );
      
cell4_pro:
   cell4
      port map
      (
      clk=>clk,
      reset=>reset,
      en_all=>en_all,
		en_init=>en_init,
      deg_r=>deg_ro3,
      deg_q=>deg_qo3,
      r=>ro3,
      q=>qo3,
      v=>vo3,
      u=>uo3,
      start=>start_o3,
      stop_i=>stop_o4,
      deg_ro=>deg_ro4,
      deg_qo=>deg_qo4,
      ro=>ro4,
      qo=>qo4,
      vo=>vo4,
      uo=>uo4,
      start_o=>start_o4,
      stop_o=>stop_i4 
      );
      
cell5_pro:
   cell5
      port map
      (
      clk=>clk,
      reset=>reset,
      en_all=>en_all,
		en_init=>en_init,
      deg_r=>deg_ro4,
      deg_q=>deg_qo4,
      r=>ro4,
      q=>qo4,
      v=>vo4,
      u=>uo4,
      start=>start_o4,
      stop_i=>stop_o5,
      deg_ro=>deg_ro5,
      deg_qo=>deg_qo5,
      ro=>ro5,