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📄 eucild_m.vhd

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💻 VHD
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123 
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    18:00:19 04/22/08
-- Design Name:    
-- Module Name:    eucild_m - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity eucild_m is
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;  -----------
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	--stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end eucild_m;

architecture Behavioral of eucild_m is

component stop_control
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	stop_i1:in std_logic;
	stop_i2:in std_logic;
	stop_i3:in std_logic;
	stop_i4:in std_logic;
	stop_i5:in std_logic;
	stop_i6:in std_logic;
	stop_i7:in std_logic;
	stop_i8:in std_logic;
	stop_i9:in std_logic;
	stop_i10:in std_logic;
	stop_i11:in std_logic;
	stop_i12:in std_logic;
	stop_i13:in std_logic;
	stop_i14:in std_logic;
	stop_i15:in std_logic;
	stop_i16:in std_logic;
	stop_i17:in std_logic;
	stop_i18:in std_logic;
	stop_i19:in std_logic;
--	stop_i20:in std_logic;
	stop_o1:out std_logic;
	stop_o2:out std_logic;
	stop_o3:out std_logic;
	stop_o4:out std_logic;
	stop_o5:out std_logic;
	stop_o6:out std_logic;
	stop_o7:out std_logic;
	stop_o8:out std_logic;
	stop_o9:out std_logic;
	stop_o10:out std_logic;
	stop_o11:out std_logic;
	stop_o12:out std_logic;
	stop_o13:out std_logic;
	stop_o14:out std_logic;
	stop_o15:out std_logic;
	stop_o16:out std_logic;
	stop_o17:out std_logic;
	stop_o18:out std_logic;
	stop_o19:out std_logic;
	stop_o20:out std_logic;
	sel:out std_logic
	);
end component;

component cell1
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell2
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell3
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell4
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell5
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell6
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell7
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell8
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell9
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell10
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell11
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell12
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell13
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell14
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	stop_i:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component cell15
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic;
123

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