bch_decoder.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    10:52:08 04/29/08
-- Design Name:    
-- Module Name:    BCH_decoder - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCH_decoder is
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	din:in std_logic_vector(7 downto 0);
	en_in:in std_logic;
	out_en:out std_logic;
	dout:out std_logic_vector(7 downto 0)
	);
end BCH_decoder;

architecture Behavioral of BCH_decoder is

component fifo_delay
	port (
	clk: IN std_logic;
	sinit: IN std_logic;
	din: IN std_logic_VECTOR(7 downto 0);
	wr_en: IN std_logic;
	rd_en: IN std_logic;
	dout: OUT std_logic_VECTOR(7 downto 0);
	full: OUT std_logic;
	empty: OUT std_logic
	);
end component;

component fifo_memory
	port (
	clk: IN std_logic;
	sinit: IN std_logic;
	din: IN std_logic_VECTOR(7 downto 0);
	wr_en: IN std_logic;
	rd_en: IN std_logic;
	dout: OUT std_logic_VECTOR(7 downto 0);
	full: OUT std_logic;
	empty: OUT std_logic;
	data_count: OUT std_logic_VECTOR(0 downto 0)  ------------------//改了
	);
end component;

component cal_s
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s1:out std_logic_vector(12 downto 0);
		  s2:out std_logic_vector(12 downto 0);
		  s3:out std_logic_vector(12 downto 0);
		  s4:out std_logic_vector(12 downto 0);
		  s5:out std_logic_vector(12 downto 0);
		  s6:out std_logic_vector(12 downto 0);
		  s7:out std_logic_vector(12 downto 0);
		  s8:out std_logic_vector(12 downto 0);
		  s9:out std_logic_vector(12 downto 0);
		  s10:out std_logic_vector(12 downto 0);
		  s11:out std_logic_vector(12 downto 0);
		  s12:out std_logic_vector(12 downto 0);
		  s13:out std_logic_vector(12 downto 0);
		  s14:out std_logic_vector(12 downto 0);
		  s15:out std_logic_vector(12 downto 0);
		  s16:out std_logic_vector(12 downto 0);
		  s17:out std_logic_vector(12 downto 0);
		  s18:out std_logic_vector(12 downto 0);
		  s19:out std_logic_vector(12 downto 0);
		  s20:out std_logic_vector(12 downto 0)
		  );
end component;

component PS
	port
	(
	 clk:in std_logic;
	 reset:in std_logic;
	 en_all:in std_logic;
	 en_load:in std_logic;
	 s1:in std_logic_vector(12 downto 0);
	 s2:in std_logic_vector(12 downto 0);
	 s3:in std_logic_vector(12 downto 0);
	 s4:in std_logic_vector(12 downto 0);
	 s5:in std_logic_vector(12 downto 0);
	 s6:in std_logic_vector(12 downto 0);
	 s7:in std_logic_vector(12 downto 0);
	 s8:in std_logic_vector(12 downto 0);
	 s9:in std_logic_vector(12 downto 0);
	 s10:in std_logic_vector(12 downto 0);
	 s11:in std_logic_vector(12 downto 0);
	 s12:in std_logic_vector(12 downto 0);
	 s13:in std_logic_vector(12 downto 0);
	 s14:in std_logic_vector(12 downto 0);
	 s15:in std_logic_vector(12 downto 0);
	 s16:in std_logic_vector(12 downto 0);
	 s17:in std_logic_vector(12 downto 0);
	 s18:in std_logic_vector(12 downto 0);
	 s19:in std_logic_vector(12 downto 0);
	 s20:in std_logic_vector(12 downto 0);
	 startout:out std_logic;
	 rout:out std_logic_vector(12 downto 0);
	 sout:out std_logic_vector(12 downto 0);
	 vout:out std_logic_vector(12 downto 0);
	 uout:out std_logic_vector(12 downto 0)
	 );
end component;

component eucild_m
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_all:in std_logic;
	en_init:in std_logic; 
	deg_r:in integer range 63 downto -63;
	deg_q:in integer range 63 downto -63;
	r:in std_logic_vector(12 downto 0);
	q:in std_logic_vector(12 downto 0);
	v:in std_logic_vector(12 downto 0);
	u:in std_logic_vector(12 downto 0);
	start:in std_logic;
	deg_ro:out integer range 63 downto -63;
	deg_qo:out integer range 63 downto -63;
	ro:out std_logic_vector(12 downto 0);
	qo:out std_logic_vector(12 downto 0);
	vo:out std_logic_vector(12 downto 0);
	uo:out std_logic_vector(12 downto 0);
	start_o:out std_logic;
	stop_o:out std_logic
	);
end component;

component SP
		port
		(
			clk:in std_logic;
			reset:in std_logic;
			en_all:in std_logic;
			en_init:in std_logic;
			v:in std_logic_vector(12 downto 0);
			v1:out std_logic_vector(12 downto 0);
			v2:out std_logic_vector(12 downto 0);
			v3:out std_logic_vector(12 downto 0);
			v4:out std_logic_vector(12 downto 0);
			v5:out std_logic_vector(12 downto 0);
			v6:out std_logic_vector(12 downto 0);
			v7:out std_logic_vector(12 downto 0);
			v8:out std_logic_vector(12 downto 0);
			v9:out std_logic_vector(12 downto 0);
			v10:out std_logic_vector(12 downto 0);
			v11:out std_logic_vector(12 downto 0)
			);
end component;

component chien
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		en_all:in std_logic;
		en_sel:in std_logic;
		out_en:out std_logic;
		err_pol0:in std_logic_vector(12 downto 0);
		err_pol1:in std_logic_vector(12 downto 0);
		err_pol2:in std_logic_vector(12 downto 0);
		err_pol3:in std_logic_vector(12 downto 0);
		err_pol4:in std_logic_vector(12 downto 0);
		err_pol5:in std_logic_vector(12 downto 0);
		err_pol6:in std_logic_vector(12 downto 0);
		err_pol7:in std_logic_vector(12 downto 0);
		err_pol8:in std_logic_vector(12 downto 0);
		err_pol9:in std_logic_vector(12 downto 0);
		err_pol10:in std_logic_vector(12 downto 0);
		sum1:out std_logic_vector(12 downto 0);
		sum2:out std_logic_vector(12 downto 0);
		sum3:out std_logic_vector(12 downto 0);
		sum4:out std_logic_vector(12 downto 0);
		sum5:out std_logic_vector(12 downto 0);
		sum6:out std_logic_vector(12 downto 0);
		sum7:out std_logic_vector(12 downto 0);
		sum8:out std_logic_vector(12 downto 0)
	);
end component;

component correct_err
	port
	(
	  clk:in std_logic;
	  reset: in std_logic;
	  en_all:in std_logic;
	  data_org:in std_logic_vector(7 downto 0);
	  sum1:in std_logic_vector(12 downto 0);
	  sum2:in std_logic_vector(12 downto 0);
	  sum3:in std_logic_vector(12 downto 0);
	  sum4:in std_logic_vector(12 downto 0);
	  sum5:in std_logic_vector(12 downto 0);
	  sum6:in std_logic_vector(12 downto 0);
	  sum7:in std_logic_vector(12 downto 0);
	  sum8:in std_logic_vector(12 downto 0);
	  data_m:out std_logic_vector(7 downto 0)				---msb_lsb---
	);
end component;

component controller
	port
	(
		clk:in std_logic;
		reset:in std_logic;
		ready:in std_logic;
		en_all_s:out std_logic;
		en_con_s:out std_logic;
		en_init_s:out std_logic;
		en_load_ps:out std_logic;
		en_all_ps:out std_logic;
		en_all_euclid:out std_logic;
		en_init_euclid:out std_logic;
		en_all_sp:out std_logic;
		en_init_sp:out std_logic;
		en_sel_chien:out std_logic;
		en_all_chien:out std_logic;
		en_all_correct:out std_logic;
		en_read_memory:out std_logic;
		en_read_delay:out std_logic;
		en_write_delay:out std_logic;
		out_en:out std_logic
	);
end component;

signal memory_out:std_logic_vector(7 downto 0);
signal ready:std_logic_VECTOR(0 downto 0);
--signal ready_fifo:std_logic_vector(14 downto 0);

signal delay_out:std_logic_vector(7 downto 0);

signal s1:std_logic_vector(12 downto 0);
signal s2:std_logic_vector(12 downto 0);
signal s3:std_logic_vector(12 downto 0);
signal s4:std_logic_vector(12 downto 0);
signal s5:std_logic_vector(12 downto 0);
signal s6:std_logic_vector(12 downto 0);
signal s7:std_logic_vector(12 downto 0);
signal s8:std_logic_vector(12 downto 0);
signal s9:std_logic_vector(12 downto 0);
signal s10:std_logic_vector(12 downto 0);
signal s11:std_logic_vector(12 downto 0);
signal s12:std_logic_vector(12 downto 0);
signal s13:std_logic_vector(12 downto 0);
signal s14:std_logic_vector(12 downto 0);
signal s15:std_logic_vector(12 downto 0);
signal s16:std_logic_vector(12 downto 0);
signal s17:std_logic_vector(12 downto 0);
signal s18:std_logic_vector(12 downto 0);
signal s19:std_logic_vector(12 downto 0);
signal s20:std_logic_vector(12 downto 0);

signal startout:std_logic;
signal rout:std_logic_vector(12 downto 0);
signal sout:std_logic_vector(12 downto 0);
signal vout:std_logic_vector(12 downto 0);
signal uout:std_logic_vector(12 downto 0);

signal vo:std_logic_vector(12 downto 0);

signal v1:std_logic_vector(12 downto 0);
signal v2:std_logic_vector(12 downto 0);
signal v3:std_logic_vector(12 downto 0);
signal v4:std_logic_vector(12 downto 0);
signal v5:std_logic_vector(12 downto 0);
signal v6:std_logic_vector(12 downto 0);
signal v7:std_logic_vector(12 downto 0);
signal v8:std_logic_vector(12 downto 0);
signal v9:std_logic_vector(12 downto 0);
signal v10:std_logic_vector(12 downto 0);
signal v11:std_logic_vector(12 downto 0);

signal sum1:std_logic_vector(12 downto 0);
signal sum2:std_logic_vector(12 downto 0);
signal sum3:std_logic_vector(12 downto 0);
signal sum4:std_logic_vector(12 downto 0);
signal sum5:std_logic_vector(12 downto 0);
signal sum6:std_logic_vector(12 downto 0);
signal sum7:std_logic_vector(12 downto 0);
signal sum8:std_logic_vector(12 downto 0);

signal en_all_s:std_logic;
signal en_con_s:std_logic;
signal en_init_s:std_logic;
signal en_load_ps:std_logic;
signal en_all_ps:std_logic;
signal en_all_euclid:std_logic;
signal en_init_euclid:std_logic;
signal en_all_sp:std_logic;
signal en_init_sp:std_logic;
signal en_sel_chien:std_logic;
signal en_all_chien:std_logic;
signal en_all_correct:std_logic;
signal en_read_memory:std_logic;
signal en_read_delay:std_logic;
signal en_write_delay:std_logic;


begin

fifo_memory_pro:
	fifo_memory
		port map
		(
		clk=>clk,
		sinit=>reset,------
		din=>din,
		wr_en=>en_in,
		rd_en=>en_read_memory,
		dout=>memory_out,
		full=>open,
		empty=>open,
		data_count=>ready    -----------------
		);

--ready(0)<=ready_fifo(13);

fifo_delay_pro:
	fifo_delay
		port map
		(
		clk=>clk,
		sinit=>reset,
		din=>memory_out,
		wr_en=>en_write_delay,
		rd_en=>en_read_delay,
		dout=>delay_out,
		full=>open,
		empty=>open
		);

cal_s_pro:
	cal_s
		port map
		(
		  clk=>clk,
		  rst=>reset,
		  en_all=>en_all_s,
		  en_con=>en_con_s,
		  en_init=>en_init_s,
		  din=>memory_out,
		  s1=>s1,
		  s2=>s2,
		  s3=>s3,
		  s4=>s4,
		  s5=>s5,
		  s6=>s6,
		  s7=>s7,
		  s8=>s8,
		  s9=>s9,
		  s10=>s10,
		  s11=>s11,
		  s12=>s12,
		  s13=>s13,
		  s14=>s14,
		  s15=>s15,
		  s16=>s16,
		  s17=>s17,
		  s18=>s18,
		  s19=>s19,
		  s20=>s20
		);

PS_pro:
	PS
	port map
	(
	 clk=>clk,
	 reset=>reset,
	 en_all=>en_all_ps,
	 en_load=>en_load_ps,
		  s1=>s1,
		  s2=>s2,
		  s3=>s3,
		  s4=>s4,
		  s5=>s5,
		  s6=>s6,
		  s7=>s7,
		  s8=>s8,
		  s9=>s9,
		  s10=>s10,
		  s11=>s11,
		  s12=>s12,
		  s13=>s13,
		  s14=>s14,
		  s15=>s15,
		  s16=>s16,
		  s17=>s17,
		  s18=>s18,
		  s19=>s19,
		  s20=>s20,
	 startout=>startout,
	 rout=>rout,
	 sout=>sout,
	 vout=>vout,
	 uout=>uout
	);

euclid_m_pro:
	eucild_m
		port map
		(
		clk=>clk,
		reset=>reset,
		en_all=>en_all_euclid,
		en_init=>en_init_euclid, 
		deg_r=>20,
		deg_q=>19,
		r=>rout,
		q=>sout,
		v=>vout,
		u=>uout,
		start=>startout,
		deg_ro=>open,
		deg_qo=>open,
		ro=>open,
		qo=>open,
		vo=>vo,
		uo=>open,
		start_o=>open,
		stop_o=>open
		);

SP_pro:
	SP
	  port map
	  (
	 	   clk=>clk,
			reset=>reset,
			en_all=>en_all_sp,
			en_init=>en_init_sp,
			v=>vo,
			v1=>v1,
			v2=>v2,
			v3=>v3,
			v4=>v4,
			v5=>v5,
			v6=>v6,
			v7=>v7,
			v8=>v8,
			v9=>v9,
			v10=>v10,
			v11=>v11
	  );

chien_pro:
	chien
		port map
		(
		clk=>clk,
		reset=>reset,
		en_all=>en_all_chien,
		en_sel=>en_sel_chien,
		out_en=>open,
		err_pol0=>v1,
		err_pol1=>v2,
		err_pol2=>v3,
		err_pol3=>v4,
		err_pol4=>v5,
		err_pol5=>v6,
		err_pol6=>v7,
		err_pol7=>v8,
		err_pol8=>v9,
		err_pol9=>v10,
		err_pol10=>v11,
		sum1=>sum1,
		sum2=>sum2,
		sum3=>sum3,
		sum4=>sum4,
		sum5=>sum5,
		sum6=>sum6,
		sum7=>sum7,
		sum8=>sum8
		);

correct_err_pro:
	correct_err
		port map
		(
	  clk=>clk,
	  reset=>reset,
	  en_all=>en_all_correct,
	  data_org=>delay_out,
	  sum1=>sum1,
		sum2=>sum2,
		sum3=>sum3,
		sum4=>sum4,
		sum5=>sum5,
		sum6=>sum6,
		sum7=>sum7,
		sum8=>sum8,
	   data_m=>dout
		);

controller_pro:
	controller
		port map
		(
		clk=>clk,
		reset=>reset,
		ready=>ready(0),
		en_all_s=>en_all_s,
		en_con_s=>en_con_s,
		en_init_s=>en_init_s,
		en_load_ps=>en_load_ps,
		en_all_ps=>en_all_ps,
		en_all_euclid=>en_all_euclid,
		en_init_euclid=>en_init_euclid,
		en_all_sp=>en_all_sp,
		en_init_sp=>en_init_sp,
		en_sel_chien=>en_sel_chien,
		en_all_chien=>en_all_chien,
		en_all_correct=>en_all_correct,
		en_read_memory=>en_read_memory,
		en_read_delay=>en_read_delay,
		en_write_delay=>en_write_delay,
		out_en=>out_en
		);

end Behavioral;