sgn.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    08:39:23 02/28/08
-- Design Name:    
-- Module Name:    sgn - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sgn is
	port(
			clk_sgn:in std_logic;
		   reset_sgn:in std_logic;
			en_in:in std_logic;
			
			in1:in std_logic_vector(15 downto 0);	 --code1
			in2:in std_logic_vector(15 downto 0);	 --code2
			in3:in std_logic_vector(15 downto 0);
			in4:in std_logic_vector(15 downto 0);
			in5:in std_logic_vector(15 downto 0);
			in6:in std_logic_vector(15 downto 0);
			in7:in std_logic_vector(15 downto 0);
			in8:in std_logic_vector(15 downto 0);
			
			awgn1:in std_logic_vector(15 downto 0);   --awgn
			awgn2:in std_logic_vector(15 downto 0); 
			awgn3:in std_logic_vector(15 downto 0); 
			awgn4:in std_logic_vector(15 downto 0); 
			awgn5:in std_logic_vector(15 downto 0); 
			awgn6:in std_logic_vector(15 downto 0); 
			awgn7:in std_logic_vector(15 downto 0); 
			awgn8:in std_logic_vector(15 downto 0); 

			data_out:out std_logic_vector(7 downto 0);
			en_out:out std_logic
			 );
end sgn;

architecture Behavioral of sgn is

signal out_tmp1:std_logic_vector(16 downto 0);
signal out_tmp2:std_logic_vector(16 downto 0);
signal out_tmp3:std_logic_vector(16 downto 0);
signal out_tmp4:std_logic_vector(16 downto 0);
signal out_tmp5:std_logic_vector(16 downto 0);
signal out_tmp6:std_logic_vector(16 downto 0);
signal out_tmp7:std_logic_vector(16 downto 0);
signal out_tmp8:std_logic_vector(16 downto 0);

signal out_tmp11:std_logic_vector(16 downto 0);
signal out_tmp22:std_logic_vector(16 downto 0);
signal out_tmp33:std_logic_vector(16 downto 0);
signal out_tmp44:std_logic_vector(16 downto 0);
signal out_tmp55:std_logic_vector(16 downto 0);
signal out_tmp66:std_logic_vector(16 downto 0);
signal out_tmp77:std_logic_vector(16 downto 0);
signal out_tmp88:std_logic_vector(16 downto 0);

signal awgn_tmp11:std_logic_vector(16 downto 0);
signal awgn_tmp22:std_logic_vector(16 downto 0);
signal awgn_tmp33:std_logic_vector(16 downto 0);
signal awgn_tmp44:std_logic_vector(16 downto 0);
signal awgn_tmp55:std_logic_vector(16 downto 0);
signal awgn_tmp66:std_logic_vector(16 downto 0);
signal awgn_tmp77:std_logic_vector(16 downto 0);
signal awgn_tmp88:std_logic_vector(16 downto 0);

signal en:std_logic;

begin
	process(clk_sgn,reset_sgn)
		begin
			if(reset_sgn='1')then
				en<='0';
				en_out<='0';
			elsif(clk_sgn'event and clk_sgn='1')then
				en<=en_in;
				en_out<=en;
			end if;
	end process;

	process(clk_sgn,reset_sgn)
		begin
		if(reset_sgn='1')then
			data_out(0)<='0';
			out_tmp1<=(others=>'0');
		elsif (clk_sgn'event and clk_sgn='1') then
			    out_tmp1<=out_tmp11 +awgn_tmp11;
				 data_out(0)<=not out_tmp1(16);
		end if;
	end process;

	process(clk_sgn,reset_sgn)
		begin
		if(reset_sgn='1')then
			data_out(1)<='0';
			out_tmp2<=(others=>'0');
		elsif (clk_sgn'event and clk_sgn='1') then
					out_tmp2<=out_tmp22 + awgn_tmp22;
					data_out(1)<=not out_tmp2(16);
		end if;
	end process;

	process(clk_sgn,reset_sgn)
		begin
		if(reset_sgn='1')then
			data_out(2)<='0';
			out_tmp3<=(others=>'0');
		elsif (clk_sgn'event and clk_sgn='1') then
					out_tmp3<=out_tmp33 + awgn_tmp33;
					data_out(2)<=not out_tmp3(16);
		end if;
	end process;

	process(clk_sgn,reset_sgn)
		begin
		if(reset_sgn='1')then
			data_out(3)<='0';
			out_tmp4<=(others=>'0');
		elsif (clk_sgn'event and clk_sgn='1') then
					out_tmp4<=out_tmp44 + awgn_tmp44;
					data_out(3)<=not out_tmp4(16);
		end if;
	end process;

	process(clk_sgn,reset_sgn)
		begin
		if(reset_sgn='1')then
			data_out(4)<='0';
			out_tmp5<=(others=>'0');
		elsif (clk_sgn'event and clk_sgn='1') then
					out_tmp5<=out_tmp55 + awgn_tmp55;
					data_out(4)<=not out_tmp5(16);
		end if;
	end process;

	process(clk_sgn,reset_sgn)
		begin
		if(reset_sgn='1')then
			data_out(5)<='0';
			out_tmp6<=(others=>'0');
		elsif (clk_sgn'event and clk_sgn='1') then
					out_tmp6<=out_tmp66 + awgn_tmp66;
					data_out(5)<=not out_tmp6(16);
		end if;
	end process;

	process(clk_sgn,reset_sgn)
		begin
		if(reset_sgn='1')then
			data_out(6)<='0';
			out_tmp7<=(others=>'0');
		elsif (clk_sgn'event and clk_sgn='1') then
					out_tmp7<=out_tmp77+ awgn_tmp77;
					data_out(6)<=not out_tmp7(16);
		end if;
	end process;

	process(clk_sgn,reset_sgn)
		begin
		if(reset_sgn='1')then
			data_out(7)<='0';
			out_tmp8<=(others=>'0');
		elsif (clk_sgn'event and clk_sgn='1') then
					out_tmp8<=out_tmp88 + awgn_tmp88;
					data_out(7)<=not out_tmp8(16);
		end if;
	end process;

out_tmp11<=in1(15)&in1;
out_tmp22<=in2(15)&in2;
out_tmp33<=in3(15)&in3;
out_tmp44<=in4(15)&in4;
out_tmp55<=in5(15)&in5;
out_tmp66<=in6(15)&in6;
out_tmp77<=in7(15)&in7;
out_tmp88<=in8(15)&in8;

awgn_tmp11<=awgn1(15)&awgn1;
awgn_tmp22<=awgn2(15)&awgn2;
awgn_tmp33<=awgn3(15)&awgn3;
awgn_tmp44<=awgn4(15)&awgn4;
awgn_tmp55<=awgn5(15)&awgn5;
awgn_tmp66<=awgn6(15)&awgn6;
awgn_tmp77<=awgn7(15)&awgn7;
awgn_tmp88<=awgn8(15)&awgn8;



 	
end Behavioral;