data_pro.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    18:50:43 05/04/08
-- Design Name:    
-- Module Name:    data_pro - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity data_pro is
	port(
		clk:in std_logic;
		reset:in std_logic;
		en_in:in std_logic;
		data_in:in std_logic_vector(7 downto 0);
		data_out:out std_logic_vector(7 downto 0);
		en_out:out std_logic
		);
end data_pro;

architecture Behavioral of data_pro is

component sgn
	port(
			clk_sgn:in std_logic;
		   reset_sgn:in std_logic;
			en_in:in std_logic;
			
			in1:in std_logic_vector(15 downto 0);	 --code1
			in2:in std_logic_vector(15 downto 0);	 --code2
			in3:in std_logic_vector(15 downto 0);
			in4:in std_logic_vector(15 downto 0);
			in5:in std_logic_vector(15 downto 0);
			in6:in std_logic_vector(15 downto 0);
			in7:in std_logic_vector(15 downto 0);
			in8:in std_logic_vector(15 downto 0);
			
			awgn1:in std_logic_vector(15 downto 0);   --awgn
			awgn2:in std_logic_vector(15 downto 0); 
			awgn3:in std_logic_vector(15 downto 0); 
			awgn4:in std_logic_vector(15 downto 0); 
			awgn5:in std_logic_vector(15 downto 0); 
			awgn6:in std_logic_vector(15 downto 0); 
			awgn7:in std_logic_vector(15 downto 0); 
			awgn8:in std_logic_vector(15 downto 0); 

			data_out:out std_logic_vector(7 downto 0);
			en_out:out std_logic
			 );
end component;

component data_map
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	en_in:in std_logic;
	data_in:in std_logic_vector(7 downto 0);
	en_out:out std_logic;
	data_out0:out std_logic_vector(15 downto 0);	
	data_out1:out std_logic_vector(15 downto 0);
	data_out2:out std_logic_vector(15 downto 0);
	data_out3:out std_logic_vector(15 downto 0);
	data_out4:out std_logic_vector(15 downto 0);
	data_out5:out std_logic_vector(15 downto 0);
	data_out6:out std_logic_vector(15 downto 0);
	data_out7:out std_logic_vector(15 downto 0)
	);
end component;	

signal tmp1:std_logic_vector(15 downto 0);
signal tmp2:std_logic_vector(15 downto 0);
signal tmp3:std_logic_vector(15 downto 0);
signal tmp4:std_logic_vector(15 downto 0);
signal tmp5:std_logic_vector(15 downto 0);
signal tmp6:std_logic_vector(15 downto 0);
signal tmp7:std_logic_vector(15 downto 0);
signal tmp8:std_logic_vector(15 downto 0);

signal en_data_map:std_logic;

begin

data_map_pro:
	data_map
		port map
		(
	clk=>clk,
	reset=>reset,
	en_in=>en_in,
	data_in=>data_in,
	en_out=>en_data_map,
	data_out0=>tmp1,	
	data_out1=>tmp2,
	data_out2=>tmp3,
	data_out3=>tmp4,
	data_out4=>tmp5,
	data_out5=>tmp6,
	data_out6=>tmp7,
	data_out7=>tmp8
	);

sgn_pro:
	sgn
		port map
		(
			clk_sgn=>clk,
		   reset_sgn=>reset,
			en_in=>en_data_map,
			
			in1=>tmp1,	 --code1
			in2=>tmp2, --code2
			in3=>tmp3,
			in4=>tmp4,
			in5=>tmp5,
			in6=>tmp6,
			in7=>tmp7,
			in8=>tmp8,
			
			awgn1=>(others=>'0'),   --awgn
			awgn2=>(others=>'0'),
			awgn3=>(others=>'0'),
			awgn4=>(others=>'0'), 
			awgn5=>(others=>'0'),
			awgn6=>(others=>'0'), 
			awgn7=>(others=>'0'), 
			awgn8=>(others=>'0'),

			data_out=>data_out,
			en_out=>en_out
			);

end Behavioral;