cal_s.vhd

bch 编码和译码

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    10:21:10 04/02/08
-- Design Name:    
-- Module Name:    cal_s - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cal_s is
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s1:out std_logic_vector(12 downto 0);
		  s2:out std_logic_vector(12 downto 0);
		  s3:out std_logic_vector(12 downto 0);
		  s4:out std_logic_vector(12 downto 0);
		  s5:out std_logic_vector(12 downto 0);
		  s6:out std_logic_vector(12 downto 0);
		  s7:out std_logic_vector(12 downto 0);
		  s8:out std_logic_vector(12 downto 0);
		  s9:out std_logic_vector(12 downto 0);
		  s10:out std_logic_vector(12 downto 0);
		  s11:out std_logic_vector(12 downto 0);
		  s12:out std_logic_vector(12 downto 0);
		  s13:out std_logic_vector(12 downto 0);
		  s14:out std_logic_vector(12 downto 0);
		  s15:out std_logic_vector(12 downto 0);
		  s16:out std_logic_vector(12 downto 0);
		  s17:out std_logic_vector(12 downto 0);
		  s18:out std_logic_vector(12 downto 0);
		  s19:out std_logic_vector(12 downto 0);
		  s20:out std_logic_vector(12 downto 0)
		  );
end cal_s;

architecture Behavioral of cal_s is

component cal_s1
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s1:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s2
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s2:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s3
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s3:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s4
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s4:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s5
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s5:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s6
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s6:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s7
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s7:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s8
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s8:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s9
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s9:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s10
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s10:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s11
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s11:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s12
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s12:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s13
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s13:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s14
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s14:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s15
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s15:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s16
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s16:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s17
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s17:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s18
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s18:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s19
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s19:out std_logic_vector(12 downto 0)
		  );
end component;

component cal_s20
	port(
		  clk:in std_logic;
		  rst:in std_logic;
		  en_all:in std_logic;
		  en_con:in std_logic;
		  en_init:in std_logic;
		  din:in std_logic_vector(7 downto 0);
		  s20:out std_logic_vector(12 downto 0)
		  );
end component;


begin

cal_s1_pro:
		cal_s1
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s1=>s1
				);
cal_s2_pro:
		cal_s2
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s2=>s2
				);
cal_s3_pro:
		cal_s3
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s3=>s3
				);
cal_s4_pro:
		cal_s4
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s4=>s4
				);
cal_s5_pro:
		cal_s5
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s5=>s5
				);
cal_s6_pro:
		cal_s6
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s6=>s6
				);
cal_s7_pro:
		cal_s7
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s7=>s7
				);
cal_s8_pro:
		cal_s8
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s8=>s8
				);
cal_s9_pro:
		cal_s9
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s9=>s9
				);
cal_s10_pro:
		cal_s10
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s10=>s10
				);
cal_s11_pro:
		cal_s11
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s11=>s11
				);
cal_s12_pro:
		cal_s12
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s12=>s12
				);
cal_s13_pro:
		cal_s13
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s13=>s13
				);
cal_s14_pro:
		cal_s14
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s14=>s14
				);
cal_s15_pro:
		cal_s15
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s15=>s15
				);
cal_s16_pro:
		cal_s16
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s16=>s16
				);
cal_s17_pro:
		cal_s17
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s17=>s17
				);
cal_s18_pro:
		cal_s18
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s18=>s18
				);
cal_s19_pro:
		cal_s19
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s19=>s19
				);

cal_s20_pro:
		cal_s20
			port map(
				clk=>clk,
		  		rst=>rst,
		  		en_all=>en_all,
				en_con=>en_con,
				en_init=>en_init,
		  		din=>din,
		  		s20=>s20
				);

--cnt_pro:
--	process(clk,rst)
--		begin
--			if(rst='1')then
--				cnt<=0;
--			elsif(clk'event and clk='1')then
--				if (en_all='1')then
--					if cnt=512 then
--						cnt<=1;
--					else
--						cnt<=cnt+1;
--					end if;
--				end if;
--			end if;
--	end process;
--
--en_con_pro:
--	process(clk)
--		begin
--			if(clk'event and clk='1')then
--				if cnt=511 then
--					en_con<='0';
--				else
--					en_con<='1';
--				end if;
--			--	en_con_tmp<=en_con;	  ------
--			end if;
--	end process;

end Behavioral;