📄 controller.vhd
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---------------------------------------------------------------------------------- Company: -- Engineer:---- Create Date: 11:34:22 04/29/08-- Design Name: -- Module Name: controller - Behavioral-- Project Name: -- Target Device: -- Tool versions: -- Description:---- Dependencies:-- -- Revision:-- Revision 0.01 - File Created-- Additional Comments:-- --------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity controller is port ( clk:in std_logic; reset:in std_logic; ready:in std_logic; en_all_s:out std_logic; en_con_s:out std_logic; en_init_s:out std_logic; en_load_ps:out std_logic; en_all_ps:out std_logic; en_all_euclid:out std_logic; en_init_euclid:out std_logic; en_all_sp:out std_logic; en_init_sp:out std_logic; en_sel_chien:out std_logic; en_all_chien:out std_logic; en_all_correct:out std_logic; en_read_memory:out std_logic; en_read_delay:out std_logic; en_write_delay:out std_logic; out_en:out std_logic );end controller;architecture Behavioral of controller issignal cnt:integer range 1500 downto 0;constant N0:integer:=1;constant N1:integer:=2;constant N2:integer:=513;constant N3:integer:=514;constant N4:integer:=515;--constant N5:integer:=516;constant N6:integer:=516;constant N7:integer:=517;constant N8:integer:=537;constant N9:integer:=574;---constant N10:integer:=575;---constant N11:integer:=576;constant N12:integer:=589;constant N13:integer:=590;constant N14:integer:=591;constant N15:integer:=1102;----- 1103--type state_type is(idle,mem_valid,cal_s_valid,cal_s_m,cal_s_m_over,init_s,cal_s_over,init_euclid,ps_euclid_valid,euclid_valid,init_sp,init_sp_over,sp_euclid_valid,init_chien,chien_valid,correct_valid); type state_type is(idle,mem_valid,cal_s_valid,cal_s_m,cal_s_m_over,init_s,init_euclid,ps_euclid_valid,euclid_valid,init_sp,init_sp_over,sp_euclid_valid,init_chien,chien_valid,correct_valid); signal present_state,next_state:state_type;begincnt_pro: process(clk,reset) begin if(reset='1')then cnt<=0; elsif(clk'event and clk='1')then if ready='1' then if cnt=1102 then ----- cnt<=1; else cnt<=cnt+1; end if; end if; end if; end process;state_transfer_pro: process(cnt,present_state,ready,reset) --,reset begin case present_state is when idle=> en_all_s<='0'; en_con_s<='1'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='0'; en_all_euclid<='0'; en_init_euclid<='0'; ------- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='0'; en_read_delay<='0'; en_write_delay<='0'; out_en<='0'; if cnt=0 then next_state<=idle; elsif cnt=N0 then next_state<=mem_valid; end if; when mem_valid=>
if ready='1'then en_all_s<='0'; en_con_s<='1'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='0'; en_all_euclid<='0'; en_init_euclid<='1'; ---- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='1'; en_read_delay<='0'; en_write_delay<='0'; out_en<='0'; else
en_all_s<='0'; en_con_s<='1'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='0'; en_all_euclid<='0'; en_init_euclid<='0'; ----- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0';
en_all_correct<='0'; en_read_memory<='0'; en_read_delay<='0'; en_write_delay<='0'; out_en<='0';
end if; if cnt=N0 then next_state<=mem_valid; elsif cnt=N1 then next_state<=cal_s_valid; end if; when cal_s_valid=> if ready='1'then
en_all_s<='1'; en_con_s<='1'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='0'; en_all_euclid<='0'; en_init_euclid<='1'; ----- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='1'; en_read_delay<='0'; en_write_delay<='1'; out_en<='0'; else
en_all_s<='0'; en_con_s<='1'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='0'; en_all_euclid<='0'; en_init_euclid<='0'; ----- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='0'; en_read_delay<='0'; en_write_delay<='0'; out_en<='0';
end if; if cnt<N2 and cnt>=N1 then next_state<=cal_s_valid; elsif cnt=N2 then next_state<=cal_s_m; end if; when cal_s_m=>
if ready='1'then en_all_s<='1'; en_con_s<='0'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='0'; en_all_euclid<='0'; en_init_euclid<='1'; ---- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='0'; ------------------ en_read_delay<='0'; en_write_delay<='1'; out_en<='0'; else
en_all_s<='0'; en_con_s<='1'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='0'; en_all_euclid<='0'; en_init_euclid<='0'; ----- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='0'; en_read_delay<='0'; en_write_delay<='0'; out_en<='0';
end if; if cnt=N2 then next_state<=cal_s_m; elsif cnt=N3 then next_state<=cal_s_m_over; end if; when cal_s_m_over=>
if ready='1' then en_all_s<='1'; en_con_s<='1'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='0'; en_all_euclid<='0'; en_init_euclid<='1'; ------- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='0'; en_read_delay<='0'; en_write_delay<='0'; out_en<='0'; else
en_all_s<='0'; en_con_s<='1'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='0'; en_all_euclid<='0'; en_init_euclid<='0'; ----- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='0'; en_read_delay<='0'; en_write_delay<='0'; out_en<='0';
end if;
if cnt=N3 then next_state<=cal_s_m_over; elsif cnt=N4 then next_state<=init_s; end if; when init_s=>
if ready='1'then en_all_s<='1'; en_con_s<='1'; en_init_s<='1'; en_load_ps<='1'; en_all_ps<='1'; en_all_euclid<='0'; en_init_euclid<='1'; ----- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='0'; en_read_delay<='0'; en_write_delay<='0'; out_en<='0'; else
en_all_s<='0'; en_con_s<='1'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='0'; en_all_euclid<='0'; en_init_euclid<='0'; ----- en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='0'; en_read_delay<='0'; en_write_delay<='0'; out_en<='0';
end if; if cnt=N4 then next_state<=init_s; elsif cnt=N6 then next_state<=init_euclid; end if; -- when cal_s_over=>-- en_all_s<='1';-- en_con_s<='1';-- en_init_s<='0';-- en_load_ps<='0';-- en_all_ps<='1';-- en_all_euclid<='0';-- en_init_euclid<='0';-- en_all_sp<='0';-- en_init_sp<='0';-- en_sel_chien<='0';-- en_all_chien<='0';-- en_all_correct<='0';-- en_read_memory<='0'; -- en_read_delay<='0';-- en_write_delay<='0'; ---- if cnt=N5 then-- next_state<=cal_s_over;-- elsif cnt=N6 then-- next_state<=init_euclid;-- end if; when init_euclid=> if ready='1'then
en_all_s<='1'; en_con_s<='1'; en_init_s<='0'; en_load_ps<='0'; en_all_ps<='1'; en_all_euclid<='0'; en_init_euclid<='0'; ------ en_all_sp<='0'; en_init_sp<='0'; en_sel_chien<='0'; en_all_chien<='0'; en_all_correct<='0'; en_read_memory<='0'; en_read_delay<='0'; en_write_delay<='0'; out_en<='0'; else
en_all_s<='0'; en_con_s<='1';⌨️ 快捷键说明
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