📄 ps.vhd
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-- Company:
-- Engineer:
--
-- Create Date: 00:31:04 05/30/06
-- Design Name:
-- Module Name: ps - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ps is
port
(
clk:in std_logic;
reset:in std_logic;
en_all:in std_logic;
en_load:in std_logic;
s1:in std_logic_vector(12 downto 0);
s2:in std_logic_vector(12 downto 0);
s3:in std_logic_vector(12 downto 0);
s4:in std_logic_vector(12 downto 0);
s5:in std_logic_vector(12 downto 0);
s6:in std_logic_vector(12 downto 0);
s7:in std_logic_vector(12 downto 0);
s8:in std_logic_vector(12 downto 0);
s9:in std_logic_vector(12 downto 0);
s10:in std_logic_vector(12 downto 0);
s11:in std_logic_vector(12 downto 0);
s12:in std_logic_vector(12 downto 0);
s13:in std_logic_vector(12 downto 0);
s14:in std_logic_vector(12 downto 0);
s15:in std_logic_vector(12 downto 0);
s16:in std_logic_vector(12 downto 0);
s17:in std_logic_vector(12 downto 0);
s18:in std_logic_vector(12 downto 0);
s19:in std_logic_vector(12 downto 0);
s20:in std_logic_vector(12 downto 0);
startout:out std_logic;
rout:out std_logic_vector(12 downto 0);
sout:out std_logic_vector(12 downto 0);
vout:out std_logic_vector(12 downto 0);
uout:out std_logic_vector(12 downto 0)
);
end ps;
architecture Behavioral of ps is
signal cnt:integer range 31 downto 0;
signal s1_tmp:std_logic_vector(12 downto 0);
signal s2_tmp:std_logic_vector(12 downto 0);
signal s3_tmp:std_logic_vector(12 downto 0);
signal s4_tmp:std_logic_vector(12 downto 0);
signal s5_tmp:std_logic_vector(12 downto 0);
signal s6_tmp:std_logic_vector(12 downto 0);
signal s7_tmp:std_logic_vector(12 downto 0);
signal s8_tmp:std_logic_vector(12 downto 0);
signal s9_tmp:std_logic_vector(12 downto 0);
signal s10_tmp:std_logic_vector(12 downto 0);
signal s11_tmp:std_logic_vector(12 downto 0);
signal s12_tmp:std_logic_vector(12 downto 0);
signal s13_tmp:std_logic_vector(12 downto 0);
signal s14_tmp:std_logic_vector(12 downto 0);
signal s15_tmp:std_logic_vector(12 downto 0);
signal s16_tmp:std_logic_vector(12 downto 0);
signal s17_tmp:std_logic_vector(12 downto 0);
signal s18_tmp:std_logic_vector(12 downto 0);
signal s19_tmp:std_logic_vector(12 downto 0);
signal s20_tmp:std_logic_vector(12 downto 0);
begin
process(reset,clk)
begin
if(reset='1')then
cnt<=21;
startout<='1';
rout<=(others=>'0');
sout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
s1_tmp<=(others=>'0');
s2_tmp<=(others=>'0');
s3_tmp<=(others=>'0');
s4_tmp<=(others=>'0');
s5_tmp<=(others=>'0');
s6_tmp<=(others=>'0');
s7_tmp<=(others=>'0');
s8_tmp<=(others=>'0');
s9_tmp<=(others=>'0');
s10_tmp<=(others=>'0');
s11_tmp<=(others=>'0');
s12_tmp<=(others=>'0');
s13_tmp<=(others=>'0');
s14_tmp<=(others=>'0');
s15_tmp<=(others=>'0');
s16_tmp<=(others=>'0');
s17_tmp<=(others=>'0');
s18_tmp<=(others=>'0');
s19_tmp<=(others=>'0');
s20_tmp<=(others=>'0');
elsif(clk'event and clk='1')then
if en_all='1'then
if en_load='1'then
cnt<=1;
s1_tmp<=s1;
s2_tmp<=s2;
s3_tmp<=s3;
s4_tmp<=s4;
s5_tmp<=s5;
s6_tmp<=s6;
s7_tmp<=s7;
s8_tmp<=s8;
s9_tmp<=s9;
s10_tmp<=s10;
s11_tmp<=s11;
s12_tmp<=s12;
s13_tmp<=s13;
s14_tmp<=s14;
s15_tmp<=s15;
s16_tmp<=s16;
s17_tmp<=s17;
s18_tmp<=s18;
s19_tmp<=s19;
s20_tmp<=s20;
elsif cnt=31 then
cnt<=1; ---------------
else
cnt<=cnt+1;
end if;
case cnt is
-- when 1 =>
-- s1_tmp<=s1;
-- s2_tmp<=s2;
-- s3_tmp<=s3;
-- s4_tmp<=s4;
-- s5_tmp<=s5;
-- s6_tmp<=s6;
-- s7_tmp<=s7;
-- s8_tmp<=s8;
-- s9_tmp<=s9;
-- s10_tmp<=s10;
-- s11_tmp<=s11;
-- s12_tmp<=s12;
-- s13_tmp<=s13;
-- s14_tmp<=s14;
-- s15_tmp<=s15;
-- s16_tmp<=s16;
-- s17_tmp<=s17;
-- s18_tmp<=s18;
-- s19_tmp<=s19;
-- s20_tmp<=s20;
when 1 =>
startout<='0';
sout<=s20_tmp;
rout<="0000000000001";
vout<=(others=>'0');
uout<=(others=>'0');
when 2 =>
startout<='1';
sout<=s19_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 3 =>
startout<='1';
sout<=s18_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 4 =>
startout<='1';
sout<=s17_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 5 =>
startout<='1';
sout<=s16_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 6 =>
startout<='1';
sout<=s15_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 7 =>
startout<='1';
sout<=s14_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 8 =>
startout<='1';
sout<=s13_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 9 =>
startout<='1';
sout<=s12_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 10 =>
startout<='1';
sout<=s11_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 11 =>
startout<='1';
sout<=s10_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 12 =>
startout<='1';
sout<=s9_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 13 =>
startout<='1';
sout<=s8_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 14 =>
startout<='1';
sout<=s7_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 15 =>
startout<='1';
sout<=s6_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 16 =>
startout<='1';
sout<=s5_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 17 =>
startout<='1';
sout<=s4_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 18 =>
startout<='1';
sout<=s3_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 19 =>
startout<='1';
sout<=s2_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
when 20 =>
startout<='1';
sout<=s1_tmp;
rout<=(others=>'0');
vout<=(others=>'0');
uout<="0000000000001";
when others =>
startout<='1';
sout<=(others=>'0');
rout<=(others=>'0');
vout<=(others=>'0');
uout<=(others=>'0');
end case;
end if;
end if;
end process;
end Behavioral;
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