hwtest_decoder.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    20:29:37 05/04/08
-- Design Name:    
-- Module Name:    hwtest_decoder - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity hwtest_decoder is
	port(
		  clk:in std_logic;
		  reset:in std_logic;
		  en_out:out std_logic;
		  data_out:out std_logic_vector(7 downto 0)
		  );
end hwtest_decoder;

architecture Behavioral of hwtest_decoder is

component hwtest_decoder_data
	port(
   		addr: IN std_logic_VECTOR(12 downto 0);
			clk: IN std_logic;
			dout: OUT std_logic_VECTOR(7 downto 0);
			en: IN std_logic	
			);
end component;

component bch_decoder
	port
	(
	clk:in std_logic;
	reset:in std_logic;
	din:in std_logic_vector(7 downto 0);
	en_in:in std_logic;
	out_en:out std_logic;
	dout:out std_logic_vector(7 downto 0)
	);
end component;

signal data_rom:std_logic_vector(7 downto 0);
signal count_top:integer range 1280 downto 0;
constant period:integer:=1280;
constant period_data:std_logic_vector(12 downto 0):="1001111111111";	 ---5119
signal address:std_logic_vector(12 downto 0);
signal nreset:std_logic;
signal en_rom:std_logic;
signal en_decoder:std_logic;

begin
																	

hwtest_decoder_data_pro:
		hwtest_decoder_data
			port map
			(
			 addr=>address,
			 en=>en_rom,
			 clk=>clk,
			 dout=>data_rom
			);
bch_decoder_pro:
	bch_decoder
		port map
		(
		clk=>clk,
		reset=>nreset,
		din=>data_rom,
		en_in=>en_decoder,
		out_en=>en_out,
		dout=>data_out
		);


nreset<=not reset;


init_pro:
	process(clk,reset)
		begin
		if(reset='0')then
			en_rom<='0';
			en_decoder<='0';
			count_top<=0;
			address<=(others=>'0');
		elsif(clk'event and clk='1')then
			
			en_decoder<=en_rom;		--fifo的使能比rom的使能慢一时钟
--			en_rom<='1';
			if count_top=period then
				count_top<=1;
			elsif count_top<=512 then
				en_rom<='1';
				count_top<=count_top+1;
			else
				en_rom<='0';	
				count_top<=count_top+1;
			end if;
         
			if(en_rom='1')then
				if address=period_data then
					address<=(others=>'0');
            else
				    address<=address+1;
				end if;
			end if;
		end if;
	end process;

end Behavioral;