controller_encode.vhd

bch 编码和译码

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-- Company: 
-- Engineer:
--
-- Create Date:    20:54:17 03/20/08
-- Design Name:    
-- Module Name:    controller - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity controller_encode is
	port
	(
	con_clk:in std_logic;
	con_rst:in std_logic;
	con_ready:in std_logic;
	con_read:out std_logic;
	con_output:out std_logic;
	data_sample:out std_logic;
	rem_sample:out std_logic
	);
end controller_encode;


architecture Behavioral of controller_encode is
 signal con_cnt:integer range 1000 downto 0;
 signal con_cnt1:integer range 1000 downto 0;
 --signal judge:std_logic_vector(1 downto 0);
 constant N_494:integer:=494;
 constant N_495:integer:=495;
 constant N_511:integer:=511;
 constant N_512:integer:=512;
 type state_type is(state_idle,state_read,state_code,state_wait,state_init);--,state_modify);
 signal present_state,next_state:state_type;
 
 type state_type1 is(state_idle1,state_data,state_rem,state_lack,state_init1);--,state_modify1);
 signal present_state1,next_state1:state_type1;
begin

state_transfer:
	process(con_rst,con_clk)
		begin
			if(con_rst='1')then				
				con_read<='-';
				con_output<='-';
				next_state<=state_idle;
			elsif(con_clk'event and con_clk='1') then
				case present_state is
					when state_idle => con_cnt<=512;					
											 con_read<='0';con_output<='0';
											 
											 next_state<=state_init;
					
					when state_init =>con_cnt<=0;con_read<='0';con_output<='0';
														 if(con_ready='1')then
														 		next_state<=state_read;
														 else
														    	next_state<=state_init; 
														 end if;
					when state_read => if(con_ready='1')then
													if(con_cnt<N_494)then
																 next_state<=state_read;
																 con_cnt<=con_cnt+1;
																 con_read<='1';
																 con_output<='0';
													end if;
											 else
															  next_state<=state_read;
															  con_read<='0';
															  con_output<='0';
											 end if;
														 
											 if(con_cnt=N_494)then
														     next_state<=state_code;

															  con_cnt<=con_cnt+1;
											 end if;
					when state_code=>if(con_cnt <N_511 and con_cnt <N_512 and con_cnt >N_494)then
																 next_state<=state_code;
																 con_output<='1';
																 con_read<='0';
																 con_cnt<=con_cnt+1;
											elsif(con_cnt=N_511)then
																 next_state<=state_wait;

																  con_cnt<=con_cnt+1;
											 end if;													 
					when state_wait=>con_output<='0';con_read<='0';con_cnt<=con_cnt+1;
															next_state<=state_init;
												
				  end case;
				
			end if;

				present_state<=next_state;
		end process;


	
state_transfer1:
	process(con_rst,con_clk)
		begin
			if(con_rst='1')then
				con_cnt1<=512;				
				data_sample<='-';
				rem_sample<='-';
				next_state1<=state_idle1;
			elsif(con_clk'event and con_clk='1') then
				case present_state1 is
					when state_idle1 => con_cnt1<=512;				
											 data_sample<='0';rem_sample<='0';
											 
											 next_state1<=state_init1;
					
					when state_init1 =>con_cnt1<=0;data_sample<='0';rem_sample<='0';
  														  if(con_ready='1')then
														 		next_state1<=state_data;
														  else
														     next_state1<=state_init1; 
														 end if;
					when state_data =>if(con_ready='1')then
												if(con_cnt1<N_494)then
																 next_state1<=state_data;
																 data_sample<='1';
																 rem_sample<='0';
																 con_cnt1<=con_cnt1+1;
												 end if;
											 else
														       next_state1<=state_data;
																 data_sample<='0';
																 rem_sample<='0';	
											 end if;
												 if(con_cnt1=N_494)then
														   next_state1<=state_lack;
															con_cnt1<=con_cnt1+1;
												 end if;
					when state_lack=>rem_sample<='1';data_sample<='1';con_cnt1<=con_cnt1+1;
															next_state1<=state_rem;
					when state_rem=>if(con_cnt <N_512 and con_cnt >N_495)then
																next_state1<=state_rem;
																rem_sample<='1';
																 data_sample<='0';
																 con_cnt1<=con_cnt1+1;
															 elsif(con_cnt>=N_512)then
																 next_state1<=state_init1;
																 con_cnt1<=con_cnt1+1;
															end if;
				end case;
					
			end if;

				present_state1<=next_state1;
		end process;

end Behavioral;