📄 top.rpt
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8 -> - - - - - * - - * - - - * * - - | - - - - - - * * | <-- a2
9 -> - - - - - * - - - - - - - * - * | - - - - - - * * | <-- a3
40 -> * * * - * - - - - * - - - - - - | - - - - * * * * | <-- b0
11 -> * * * - * * * * * - * * * * * * | - - - - * * * - | <-- b3
45 -> - - * * * - - - - - - - - - - - | - - - - * * * - | <-- en
LC82 -> - * - - - - - - - - - - - - - - | - - - - - * * - | <-- |LED7:2|~1039~1
LC113-> * * * - * - - - - - - - - - - - | - - - - * * * - | <-- |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node1
LC68 -> * * * - * - - - - - - - - - - - | - - - - * * * - | <-- |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node2
LC69 -> * * * - * - * - - - * * * * * - | - - - - * * * - | <-- |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node3
LC126-> - - - - - * - * - - - * * * - - | - - - - - - * - | <-- |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node4
LC118-> - - - - - * - - * - - - * * - - | - - - - - - * - | <-- |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node5
LC116-> - - - - - * - - - - - - - * * - | - - - - - - * - | <-- |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node6
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\mul4\top.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----------------------------- LC117 |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|gcp2
| +--------------------------- LC114 |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|g4
| | +------------------------- LC121 |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|ps2
| | | +----------------------- LC127 |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|ps3
| | | | +--------------------- LC113 |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node1
| | | | | +------------------- LC120 |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node2
| | | | | | +----------------- LC124 |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node3
| | | | | | | +--------------- LC115 |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node4
| | | | | | | | +------------- LC119 |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | +----------- LC123 |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|g2cp1
| | | | | | | | | | +--------- LC125 |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|ps4
| | | | | | | | | | | +------- LC126 |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node4
| | | | | | | | | | | | +----- LC118 |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | | | | | +--- LC116 |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node6
| | | | | | | | | | | | | | +- LC122 |MUL4:1|LPM_ADD_SUB:265|datab_node5
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC117-> - - - - - - * - - - - - - - - | - - - - - - - * | <-- |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|gcp2
LC114-> - - - - - - - * * * - - * - - | - - - - - - - * | <-- |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|g4
LC121-> - * - - - - - - - - - - - - - | - - - - - - - * | <-- |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|ps2
LC127-> - * - - - - * - - - - - - - - | - - - - - - - * | <-- |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|ps3
LC115-> - - - - - - - - - * * * * - - | - - - - - - - * | <-- |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node4
LC119-> - - - - - - - - - * - - * * - | - - - - - - - * | <-- |MUL4:1|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node5
LC123-> - - - - - - - - - - - - - * - | - - - - - - - * | <-- |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|g2cp1
LC125-> - - - - - - - - - - - * * * - | - - - - - - - * | <-- |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|ps4
LC122-> - - - - - - - - - * - - * * - | - - - - - - - * | <-- |MUL4:1|LPM_ADD_SUB:265|datab_node5
Pin
37 -> * * - - * * - - - - - - - - - | - - - - * * * * | <-- a0
39 -> * * * - * * - - - - - - - - - | - - - - * - * * | <-- a1
8 -> * * * * - * * - - * * * * - - | - - - - - - * * | <-- a2
9 -> - * - * - - * * * * - - * - * | - - - - - - * * | <-- a3
40 -> * * * * * * * - - - - - - - - | - - - - * * * * | <-- b0
41 -> * * * * * * * * * * - - * - - | - - - - - - - * | <-- b1
5 -> - - - - - - - - - * * * * - * | - - - - * - - * | <-- b2
LC71 -> - - - - - - - - - - - * * * - | - - - - - - - * | <-- |MUL4:1|LPM_ADD_SUB:265|addcore:adder|addcore:adder0|g4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\mul4\top.rpt
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** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
en : INPUT;
-- Node name is 'led0'
-- Equation name is 'led0', location is LC094, type is output.
led0 = LCELL( _EQ001 $ GND);
_EQ001 = en & _LC084
# !en & _LC065;
-- Node name is 'led1'
-- Equation name is 'led1', location is LC093, type is output.
led1 = LCELL( _EQ002 $ GND);
_EQ002 = en & _LC090
# !en & _LC080;
-- Node name is 'led2'
-- Equation name is 'led2', location is LC091, type is output.
led2 = LCELL( _EQ003 $ GND);
_EQ003 = en & _LC076
# !en & _LC066;
-- Node name is 'led3'
-- Equation name is 'led3', location is LC088, type is output.
led3 = LCELL( _EQ004 $ GND);
_EQ004 = en & _LC087
# !en & _LC081;
-- Node name is 'led4'
-- Equation name is 'led4', location is LC086, type is output.
led4 = LCELL( _EQ005 $ GND);
_EQ005 = en & _LC092
# !en & _LC096;
-- Node name is 'led5'
-- Equation name is 'led5', location is LC085, type is output.
led5 = LCELL( _EQ006 $ GND);
_EQ006 = en & _LC103
# !en & _LC082;
-- Node name is 'led6'
-- Equation name is 'led6', location is LC083, type is output.
led6 = LCELL( _EQ007 $ GND);
_EQ007 = en & _LC110
# !en & _LC101;
-- Node name is '|LED7:2|~708~1'
-- Equation name is '_LC110', type is buried
-- synthesized logic cell
_LC110 = LCELL( _EQ008 $ VCC);
_EQ008 = a0 & b0 & _LC068 & !_LC097 & !_LC098 & !_LC104 & !_LC109 &
!_LC112 & _LC113
# a0 & b0 & !_LC068 & !_LC097 & !_LC098 & !_LC104 & !_LC109 &
!_LC112 & !_LC113
# _LC068 & !_LC097 & !_LC098 & !_LC102 & !_LC109 & !_LC112 &
!_LC113 & _X001 & _X002
# !_LC101 & _X003;
_X001 = EXP( a0 & b0);
_X002 = EXP( a0 & b3 & _LC069);
_X003 = EXP(!_LC097 & !_LC098 & !_LC109 & !_LC112);
-- Node name is '|LED7:2|~759~1'
-- Equation name is '_LC103', type is buried
-- synthesized logic cell
_LC103 = LCELL( _EQ009 $ VCC);
_EQ009 = a0 & b0 & _LC068 & !_LC097 & !_LC098 & !_LC104 & !_LC109 &
!_LC112 & !_LC113
# a0 & b0 & !_LC097 & !_LC098 & !_LC102 & !_LC109 & !_LC112 &
_LC113 & _X002
# !_LC068 & !_LC097 & !_LC098 & !_LC104 & !_LC109 & !_LC112 &
!_LC113 & _X001
# _LC068 & !_LC097 & !_LC098 & !_LC109 & !_LC112 & _X001 & _X004
# !_LC082 & _X003;
_X002 = EXP( a0 & b3 & _LC069);
_X001 = EXP( a0 & b0);
_X004 = EXP(!_LC104 & !_LC113);
_X003 = EXP(!_LC097 & !_LC098 & !_LC109 & !_LC112);
-- Node name is '|LED7:2|~810~1'
-- Equation name is '_LC092', type is buried
-- synthesized logic cell
_LC092 = LCELL( _EQ010 $ _EQ011);
_EQ010 = a0 & b0 & !_LC097 & !_LC098 & !_LC104 & !_LC109 & !_LC112
# a0 & b0 & !_LC097 & !_LC098 & !_LC109 & !_LC112 & !_LC113
# !_LC068 & !_LC097 & !_LC098 & !_LC102 & !_LC109 & !_LC112 & _X002
# _LC068 & !_LC097 & !_LC098 & !_LC104 & !_LC109 & !_LC112;
_X002 = EXP( a0 & b3 & _LC069);
_EQ011 = _LC096 & _X003;
_X003 = EXP(!_LC097 & !_LC098 & !_LC109 & !_LC112);
-- Node name is '|LED7:2|~861~1'
-- Equation name is '_LC087', type is buried
-- synthesized logic cell
_LC087 = LCELL( _EQ012 $ VCC);
_EQ012 = !_LC068 & !_LC097 & !_LC098 & !_LC102 & !_LC109 & !_LC112 &
_LC113 & _X001 & _X002
# a0 & b0 & _LC068 & !_LC097 & !_LC098 & !_LC109 & !_LC112 &
_LC113
# !_LC097 & !_LC098 & !_LC104 & !_LC109 & !_LC112 & !_LC113 & _X005
# !_LC081 & _X003;
_X001 = EXP( a0 & b0);
_X002 = EXP( a0 & b3 & _LC069);
_X005 = EXP( a0 & b0 & _LC068);
_X003 = EXP(!_LC097 & !_LC098 & !_LC109 & !_LC112);
-- Node name is '|LED7:2|~912~1'
-- Equation name is '_LC076', type is buried
-- synthesized logic cell
_LC076 = LCELL( _EQ013 $ _EQ014);
_EQ013 = !_LC097 & !_LC098 & !_LC102 & !_LC109 & !_LC112 & _LC113 & _X002
# _LC068 & !_LC097 & !_LC098 & !_LC102 & !_LC109 & !_LC112 & _X002
# !_LC097 & !_LC098 & !_LC102 & !_LC109 & !_LC112 & _X001 & _X002
# !_LC097 & !_LC098 & !_LC109 & !_LC112 & _LC113 & _X001;
_X002 = EXP( a0 & b3 & _LC069);
_X001 = EXP( a0 & b0);
_EQ014 = _LC066 & _X003;
_X003 = EXP(!_LC097 & !_LC098 & !_LC109 & !_LC112);
-- Node name is '|LED7:2|~963~1'
-- Equation name is '_LC090', type is buried
-- synthesized logic cell
_LC090 = LCELL( _EQ015 $ VCC);
_EQ015 = a0 & b0 & _LC068 & !_LC097 & !_LC098 & !_LC102 & !_LC109 &
!_LC112 & !_LC113 & _X002
# a0 & b0 & !_LC097 & !_LC098 & !_LC104 & !_LC109 & !_LC112 &
_LC113
# !_LC068 & !_LC097 & !_LC098 & !_LC104 & !_LC109 & !_LC112
# !_LC080 & _X003;
_X002 = EXP( a0 & b3 & _LC069);
_X003 = EXP(!_LC097 & !_LC098 & !_LC109 & !_LC112);
-- Node name is '|LED7:2|~1014~1'
-- Equation name is '_LC084', type is buried
-- synthesized logic cell
_LC084 = LCELL( _EQ016 $ VCC);
_EQ016 = a0 & b0 & !_LC068 & !_LC097 & !_LC098 & !_LC102 & !_LC109 &
!_LC112 & _LC113 & _X002
# a0 & b0 & _LC068 & !_LC097 & !_LC098 & !_LC102 & !_LC109 &
!_LC112 & !_LC113 & _X002
# !_LC097 & !_LC098 & !_LC104 & !_LC109 & !_LC112 & !_LC113 & _X005
# !_LC065 & _X003;
_X002 = EXP( a0 & b3 & _LC069);
_X005 = EXP( a0 & b0 & _LC068);
_X003 = EXP(!_LC097 & !_LC098 & !_LC109 & !_LC112);
-- Node name is '|LED7:2|~1033~1~2'
-- Equation name is '_LC099', type is buried
-- synthesized logic cell
_LC099 = LCELL( _EQ017 $ GND);
_EQ017 = a0 & b0 & en & _LC068 & !_LC097 & !_LC098 & !_LC102 & !_LC104 &
!_LC109 & !_LC112 & _X001 & _X002
# a0 & b0 & _LC068 & !_LC097 & !_LC098 & !_LC101 & !_LC104 &
!_LC109 & !_LC112 & _LC113
# a0 & b0 & en & !_LC097 & !_LC098 & !_LC102 & !_LC104 & !_LC109 &
!_LC112 & !_LC113 & _X001 & _X002
# a0 & b0 & !_LC068 & !_LC097 & !_LC098 & !_LC101 & !_LC104 &
!_LC109 & !_LC112 & !_LC113
# _LC068 & !_LC097 & !_LC098 & !_LC101 & !_LC102 & !_LC109 &
!_LC112 & !_LC113 & _X001 & _X002;
_X001 = EXP( a0 & b0);
_X002 = EXP( a0 & b3 & _LC069);
-- Node name is '|LED7:2|~1033~1~3'
-- Equation name is '_LC106', type is buried
-- synthesized logic cell
_LC106 = LCELL( _EQ018 $ GND);
_EQ018 = !_LC101 & _X003
# !en & !_LC101
# _LC099;
_X003 = EXP(!_LC097 & !_LC098 & !_LC109 & !_LC112);
-- Node name is '|LED7:2|~1033~1'
-- Equation name is '_LC101', type is buried
-- synthesized logic cell
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