📄 mul4.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mul4 is
port(a,b:in std_logic_vector(3 downto 0);
y:out std_logic_vector(7 downto 0));
end mul4;
architecture behav of mul4 is
signal tmp1:std_logic_vector(3 downto 0);
signal tmp2:std_logic_vector(4 downto 0);
signal tmp3:std_logic_vector(5 downto 0);
signal tmp4:std_logic_vector(6 downto 0);
begin
tmp1<=a when b(0)='1'else"0000";
tmp2<=(a &'0') when b(1)='1'else"00000";
tmp3<=(a &"00") when b(2)='1'else"000000";
tmp4<=(a &"000") when b(3)='1'else"0000000";
y<=tmp1 + tmp2 + tmp3 + ('0'&tmp4);
end behav;
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