📄 mul4.rpt
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Device-Specific Information: e:\mul4\mul4.rpt
mul4
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(24) 32 B SOFT t 0 0 0 5 1 0 1 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|gcp2
(25) 31 B SOFT t 1 1 0 6 0 0 3 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|g4
(26) 30 B SOFT t 1 0 0 4 0 0 2 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|ps2
(27) 29 B SOFT t 1 1 0 4 0 0 1 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|ps3
(32) 25 B SOFT t 3 0 1 5 1 1 2 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node2
(5) 2 A SOFT t 1 0 0 4 2 0 3 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node3
(4) 1 A SOFT t 1 0 0 2 1 0 4 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node4
(6) 3 A SOFT t 0 0 0 2 1 0 3 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node5
(12) 8 A SOFT t 2 2 0 7 3 0 1 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|g2cp1
(11) 7 A SOFT t 1 1 0 3 3 0 3 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|g4
(8) 5 A SOFT t 0 0 0 2 1 0 2 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|ps3
(18) 13 A SOFT t 1 0 0 2 1 0 3 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|ps4
(14) 10 A SOFT t 1 1 0 3 3 5 0 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node3
(13) 9 A SOFT t 1 0 0 2 3 3 2 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node4
(9) 6 A SOFT t 2 1 0 4 6 3 1 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node5
(7) 4 A SOFT t 1 1 0 0 5 1 2 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node6
(21) 16 A SOFT t 0 0 0 2 0 0 3 |LPM_ADD_SUB:265|datab_node5
(40) 18 B SOFT t 1 1 0 4 5 1 0 |LPM_ADD_SUB:274|addcore:adder|g2cp2
(39) 19 B SOFT t 1 0 0 2 1 4 0 |LPM_ADD_SUB:274|addcore:adder|ps4
(38) 20 B SOFT t 0 0 0 2 1 2 1 |LPM_ADD_SUB:274|addcore:adder|ps6
(37) 21 B SOFT t 0 0 0 2 0 1 0 |LPM_ADD_SUB:274|datab_node3
(36) 22 B SOFT t 0 0 0 2 0 3 1 |LPM_ADD_SUB:274|datab_node5
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\mul4\mul4.rpt
mul4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------------------- LC2 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node3
| +------------------------- LC1 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node4
| | +----------------------- LC3 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node5
| | | +--------------------- LC8 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|g2cp1
| | | | +------------------- LC7 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|g4
| | | | | +----------------- LC5 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|ps3
| | | | | | +--------------- LC13 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|ps4
| | | | | | | +------------- LC10 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node3
| | | | | | | | +----------- LC9 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node4
| | | | | | | | | +--------- LC6 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | | +------- LC4 |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node6
| | | | | | | | | | | +----- LC16 |LPM_ADD_SUB:265|datab_node5
| | | | | | | | | | | | +--- LC11 y0
| | | | | | | | | | | | | +- LC12 y2
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC2 -> - - - - * * - * - - - - - - | * - | <-- |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node3
LC1 -> - - - * - - * - * * - - - - | * - | <-- |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node4
LC3 -> - - - * - - - - - * * - - - | * - | <-- |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node5
LC8 -> - - - - - - - - - - * - - - | * - | <-- |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|g2cp1
LC7 -> - - - - - - - - * * * - - - | * - | <-- |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|g4
LC5 -> - - - - * - - * - - - - - - | * - | <-- |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|ps3
LC13 -> - - - - - - - - * * * - - - | * - | <-- |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|ps4
LC16 -> - - - * - - - - - * * - - - | * - | <-- |LPM_ADD_SUB:265|datab_node5
Pin
4 -> - - - * * - - * - - - - * * | * * | <-- a0
8 -> - - - * * * - * - - - - - - | * * | <-- a1
9 -> * - - * - - * - * * - - - - | * * | <-- a2
11 -> * * * * - - - - - * - * - - | * * | <-- a3
6 -> * - - * - - - - - - - - * - | * * | <-- b0
5 -> * * * * - - - - - * - - - - | * * | <-- b1
12 -> - - - * * * * * * * - * - * | * - | <-- b2
LC32 -> * - - - - - - - - - - - - - | * - | <-- |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|gcp2
LC31 -> - * * - - - - - - * - - - - | * - | <-- |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|g4
LC29 -> * - - - - - - - - - - - - - | * - | <-- |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|ps3
LC25 -> - - - - * - - * - - - - - * | * - | <-- |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\mul4\mul4.rpt
mul4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC32 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|gcp2
| +----------------------------- LC31 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|g4
| | +--------------------------- LC30 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|ps2
| | | +------------------------- LC29 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|ps3
| | | | +----------------------- LC25 |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|result_node2
| | | | | +--------------------- LC18 |LPM_ADD_SUB:274|addcore:adder|g2cp2
| | | | | | +------------------- LC19 |LPM_ADD_SUB:274|addcore:adder|ps4
| | | | | | | +----------------- LC20 |LPM_ADD_SUB:274|addcore:adder|ps6
| | | | | | | | +--------------- LC21 |LPM_ADD_SUB:274|datab_node3
| | | | | | | | | +------------- LC22 |LPM_ADD_SUB:274|datab_node5
| | | | | | | | | | +----------- LC23 y1
| | | | | | | | | | | +--------- LC28 y3
| | | | | | | | | | | | +------- LC24 y4
| | | | | | | | | | | | | +----- LC26 y5
| | | | | | | | | | | | | | +--- LC27 y6
| | | | | | | | | | | | | | | +- LC17 y7
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC30 -> * - - - * - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:264|addcore:adder|addcore:adder0|ps2
LC18 -> - - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:274|addcore:adder|g2cp2
LC19 -> - - - - - - - - - - - - * * * * | - * | <-- |LPM_ADD_SUB:274|addcore:adder|ps4
LC20 -> - - - - - * - - - - - - - - * * | - * | <-- |LPM_ADD_SUB:274|addcore:adder|ps6
LC21 -> - - - - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:274|datab_node3
LC22 -> - - - - - * - - - - - - - * * * | - * | <-- |LPM_ADD_SUB:274|datab_node5
Pin
4 -> * * - - * - - - * - * * * * * * | * * | <-- a0
8 -> * * * - * * * - - - * - * * * - | * * | <-- a1
9 -> * * * * * * - - - * - - - * * - | * * | <-- a2
11 -> - * - * - * - * - - - - - - * - | * * | <-- a3
6 -> * * * * * - - - - - * - - - - - | * * | <-- b0
5 -> * * * * * - - - - - * - - - - - | * * | <-- b1
14 -> - - - - - * * * * * - * * * * * | - * | <-- b3
LC10 -> - - - - - - - - - - - * * * * * | - * | <-- |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node3
LC9 -> - - - - - * * - - - - - * * * - | - * | <-- |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node4
LC6 -> - - - - - * - - - - - - - * * * | - * | <-- |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node5
LC4 -> - - - - - * - * - - - - - - * - | - * | <-- |LPM_ADD_SUB:265|addcore:adder|addcore:adder0|result_node6
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\mul4\mul4.rpt
mul4
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', location is LC011, type is output.
y0 = LCELL( _EQ001 $ GND);
_EQ001 = a0 & b0;
-- Node name is 'y1'
-- Equation name is 'y1', location is LC023, type is output.
y1 = LCELL( _EQ002 $ _EQ003);
_EQ002 = a1 & b0;
_EQ003 = a0 & b1;
-- Node name is 'y2'
-- Equation name is 'y2', location is LC012, type is output.
y2 = LCELL( _EQ004 $ _LC025);
_EQ004 = a0 & b2;
-- Node name is 'y3'
-- Equation name is 'y3', location is LC028, type is output.
y3 = LCELL( _EQ005 $ GND);
_EQ005 = _X001 & _X002;
_X001 = EXP( a0 & b3 & _LC010);
_X002 = EXP(!_LC010 & !_LC021);
-- Node name is 'y4'
-- Equation name is 'y4', location is LC024, type is output.
y4 = LCELL( _EQ006 $ _EQ007);
_EQ006 = !_LC019 & _X003;
_X003 = EXP( a1 & b3 & _LC009);
_EQ007 = a0 & b3 & _LC010;
-- Node name is 'y5'
-- Equation name is 'y5', location is LC026, type is output.
y5 = LCELL( _EQ008 $ _EQ009);
_EQ008 = a0 & b3 & _LC010 & !_LC019
# a1 & b3 & _LC009;
_EQ009 = _X004 & _X005;
_X004 = EXP( a2 & b3 & _LC006);
_X005 = EXP(!_LC006 & !_LC022);
-- Node name is 'y6'
-- Equation name is 'y6', location is LC027, type is output.
y6 = LCELL( _EQ010 $ _EQ011);
_EQ010 = a0 & b3 & _LC010 & !_LC019 & _X005
# a1 & b3 & _LC009 & _X005
# a2 & b3 & _LC006;
_X005 = EXP(!_LC006 & !_LC022);
_EQ011 = !_LC020 & _X006;
_X006 = EXP( a3 & b3 & _LC004);
-- Node name is 'y7'
-- Equation name is 'y7', location is LC017, type is output.
y7 = LCELL( _EQ012 $ _LC018);
_EQ012 = a0 & b3 & _LC010 & !_LC018 & !_LC019 & !_LC020 & _X005;
_X005 = EXP(!_LC006 & !_LC022);
-- Node name is '|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( _EQ013 $ GND);
_EQ013 = a0 & a1 & b0 & b1 & !_LC030
# a1 & a2 & b0 & b1;
-- Node name is '|LPM_ADD_SUB:264|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( _EQ014 $ GND);
_EQ014 = a0 & a1 & !a2 & a3 & b0 & b1 & _X007
# !a1 & a2 & a3 & b0 & b1
# a1 & a2 & b0 & b1;
_X007 = EXP( a2 & b1);
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