mul4.rpt

分析二进制乘法中计算步骤（多少次加法

Project Information                                           e:\mul4\mul4.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/19/2006 19:57:29

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


MUL4


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

mul4      EPM7032SLC44-5   8        8        0      30      19          93 %

User Pins:                 8        8        0  



Project Information                                           e:\mul4\mul4.rpt

** FILE HIERARCHY **



|lpm_add_sub:264|
|lpm_add_sub:264|addcore:adder|
|lpm_add_sub:264|addcore:adder|addcore:adder0|
|lpm_add_sub:264|altshift:result_ext_latency_ffs|
|lpm_add_sub:264|altshift:carry_ext_latency_ffs|
|lpm_add_sub:264|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:265|
|lpm_add_sub:265|addcore:adder|
|lpm_add_sub:265|addcore:adder|addcore:adder0|
|lpm_add_sub:265|altshift:result_ext_latency_ffs|
|lpm_add_sub:265|altshift:carry_ext_latency_ffs|
|lpm_add_sub:265|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:274|
|lpm_add_sub:274|addcore:adder|
|lpm_add_sub:274|altshift:result_ext_latency_ffs|
|lpm_add_sub:274|altshift:carry_ext_latency_ffs|
|lpm_add_sub:274|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                                  e:\mul4\mul4.rpt
mul4

***** Logic for device 'mul4' compiled without errors.




Device: EPM7032SLC44-5

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff



Device-Specific Information:                                  e:\mul4\mul4.rpt
mul4

** ERROR SUMMARY **

Info: Chip 'mul4' in device 'EPM7032SLC44-5' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                            R  
                                            E  
                                            S  
                                            E  
                                            R  
                       V  G  G  G  G  G     V  
              b  b  a  C  N  N  N  N  N  y  E  
              0  1  0  C  D  D  D  D  D  7  D  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
    #TDI |  7                                39 | RESERVED 
      a1 |  8                                38 | #TDO 
      a2 |  9                                37 | RESERVED 
     GND | 10                                36 | RESERVED 
      a3 | 11                                35 | VCC 
      b2 | 12         EPM7032SLC44-5         34 | y1 
    #TMS | 13                                33 | y4 
      b3 | 14                                32 | #TCK 
     VCC | 15                                31 | y5 
      y0 | 16                                30 | GND 
      y2 | 17                                29 | y6 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              R  R  R  R  G  V  R  R  R  R  y  
              E  E  E  E  N  C  E  E  E  E  3  
              S  S  S  S  D  C  S  S  S  S     
              E  E  E  E        E  E  E  E     
              R  R  R  R        R  R  R  R     
              V  V  V  V        V  V  V  V     
              E  E  E  E        E  E  E  E     
              D  D  D  D        D  D  D  D     


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                                  e:\mul4\mul4.rpt
mul4

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    14/16( 87%)  12/16( 75%)   8/16( 50%)  19/36( 52%) 
B:    LC17 - LC32    16/16(100%)   8/16( 50%)  12/16( 75%)  17/36( 47%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            20/32     ( 62%)
Total logic cells used:                         30/32     ( 93%)
Total shareable expanders used:                 19/32     ( 59%)
Total Turbo logic cells used:                   30/32     ( 93%)
Total shareable expanders not available (n/a):   1/32     (  3%)
Average fan-in:                                  5.16
Total fan-in:                                   155

Total input pins required:                       8
Total fast input logic cells required:           0
Total output pins required:                      8
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     30
Total flipflops required:                        0
Total product terms required:                   81
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          18

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:                                  e:\mul4\mul4.rpt
mul4

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   4    (1)  (A)      INPUT               0      0   0    0    0    8    7  a0
   8    (5)  (A)      INPUT               0      0   0    0    0    4   10  a1
   9    (6)  (A)      INPUT               0      0   0    0    0    2   12  a2
  11    (7)  (A)      INPUT               0      0   0    0    0    1   10  a3
   6    (3)  (A)      INPUT               0      0   0    0    0    2    7  b0
   5    (2)  (A)      INPUT               0      0   0    0    0    1   10  b1
  12    (8)  (A)      INPUT               0      0   0    0    0    1    8  b2
  14   (10)  (A)      INPUT               0      0   0    0    0    5    5  b3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                  e:\mul4\mul4.rpt
mul4

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  16     11    A     OUTPUT      t        0      0   0    2    0    0    0  y0
  34     23    B     OUTPUT      t        0      0   0    4    0    0    0  y1
  17     12    A     OUTPUT      t        0      0   0    2    1    0    0  y2
  28     28    B     OUTPUT      t        2      0   0    2    2    0    0  y3
  33     24    B     OUTPUT      t        1      0   0    3    3    0    0  y4
  31     26    B     OUTPUT      t        2      1   0    4    5    0    0  y5
  29     27    B     OUTPUT      t        2      1   0    5    7    0    0  y6
  41     17    B     OUTPUT      t        1      1   0    2    6    0    0  y7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell