📄 top.rpt
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Shareable
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
10 6 A FF t 0 0 0 1 2 0 0 ser_out
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\p2s\top.rpt
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** BURIED LOGIC **
Shareable
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 1 A TFFE + t 0 0 0 0 1 1 5 |DIV:1|count1 (|DIV:1|:6)
- 2 A TFFE + t 0 0 0 0 0 0 1 |DIV:1|count0 (|DIV:1|:7)
(9) 8 A DFFE t 0 0 0 2 2 1 0 |P2S:2|para4 (|P2S:2|:10)
- 7 A DFFE t 0 0 0 2 2 0 1 |P2S:2|para3 (|P2S:2|:11)
(11) 5 A DFFE t 0 0 0 2 2 0 1 |P2S:2|para2 (|P2S:2|:12)
- 4 A DFFE t 0 0 0 2 2 0 1 |P2S:2|para1 (|P2S:2|:13)
(12) 3 A DFFE t 0 0 0 2 1 0 1 |P2S:2|para0 (|P2S:2|:14)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\p2s\top.rpt
top
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC1 |DIV:1|count1
| +------------- LC2 |DIV:1|count0
| | +----------- LC8 |P2S:2|para4
| | | +--------- LC7 |P2S:2|para3
| | | | +------- LC5 |P2S:2|para2
| | | | | +----- LC4 |P2S:2|para1
| | | | | | +--- LC3 |P2S:2|para0
| | | | | | | +- LC6 ser_out
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC1 -> * - * * * * * * | * - - - - - - - | <-- |DIV:1|count1
LC2 -> * * - - - - - - | * - - - - - - - | <-- |DIV:1|count0
LC8 -> - - - - - - - * | * - - - - - - - | <-- |P2S:2|para4
LC7 -> - - * - - - - - | * - - - - - - - | <-- |P2S:2|para3
LC5 -> - - - * - - - - | * - - - - - - - | <-- |P2S:2|para2
LC4 -> - - - - * - - - | * - - - - - - - | <-- |P2S:2|para1
LC3 -> - - - - - * - - | * - - - - - - - | <-- |P2S:2|para0
Pin
83 -> - - - - - - - - | - - - - - - - - | <-- clk
37 -> - - * * * * * * | * - - - - - - - | <-- go
39 -> - - - - - - * - | * - - - - - - - | <-- par_in0
40 -> - - - - - * - - | * - - - - - - - | <-- par_in1
41 -> - - - - * - - - | * - - - - - - - | <-- par_in2
44 -> - - - * - - - - | * - - - - - - - | <-- par_in3
45 -> - - * - - - - - | * - - - - - - - | <-- par_in4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\p2s\top.rpt
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** EQUATIONS **
clk : INPUT;
go : INPUT;
par_in0 : INPUT;
par_in1 : INPUT;
par_in2 : INPUT;
par_in3 : INPUT;
par_in4 : INPUT;
-- Node name is 'ser_out' = '|P2S:2|:8'
-- Equation name is 'ser_out', type is output
ser_out = DFFE( _LC008 $ GND, _LC001, !go, VCC, VCC);
-- Node name is '|DIV:1|:7' = '|DIV:1|count0'
-- Equation name is '_LC002', type is buried
_LC002 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|DIV:1|:6' = '|DIV:1|count1'
-- Equation name is '_LC001', type is buried
_LC001 = TFFE( _LC002, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|P2S:2|:14' = '|P2S:2|para0'
-- Equation name is '_LC003', type is buried
_LC003 = DFFE( GND $ GND, _LC001, !_EQ001, !_EQ002, VCC);
_EQ001 = go & !par_in0;
_EQ002 = go & par_in0;
-- Node name is '|P2S:2|:13' = '|P2S:2|para1'
-- Equation name is '_LC004', type is buried
_LC004 = DFFE( _LC003 $ GND, _LC001, !_EQ003, !_EQ004, VCC);
_EQ003 = go & !par_in1;
_EQ004 = go & par_in1;
-- Node name is '|P2S:2|:12' = '|P2S:2|para2'
-- Equation name is '_LC005', type is buried
_LC005 = DFFE( _LC004 $ GND, _LC001, !_EQ005, !_EQ006, VCC);
_EQ005 = go & !par_in2;
_EQ006 = go & par_in2;
-- Node name is '|P2S:2|:11' = '|P2S:2|para3'
-- Equation name is '_LC007', type is buried
_LC007 = DFFE( _LC005 $ GND, _LC001, !_EQ007, !_EQ008, VCC);
_EQ007 = go & !par_in3;
_EQ008 = go & par_in3;
-- Node name is '|P2S:2|:10' = '|P2S:2|para4'
-- Equation name is '_LC008', type is buried
_LC008 = DFFE( _LC007 $ GND, _LC001, !_EQ009, !_EQ010, VCC);
_EQ009 = go & !par_in4;
_EQ010 = go & par_in4;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\p2s\top.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,047K
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