p2s.vhd

来自「并串转换器：将并行输入的信号以串行方式输出」· VHDL 代码 · 共 39 行

library ieee;
use ieee.std_logic_1164.all;

entity p2s is
port(par_in:in std_logic_vector(4 downto 0);
     clk,go:in std_logic;
     ser_out:out std_logic);
end p2s;

architecture behav of p2s is 
signal para:std_logic_vector(4 downto 0);
begin

process(clk)
begin
if(go='1')then

para<=par_in;
elsif((clk'event)and(clk='1'))then 
--para(1)<=para(0);

para<=para(3 downto 0) & '0';
--for i in 1 to 4 loop
--para(i)<=para(i-1);
--end loop;
end if;
end process;

process(clk)
begin
if(go='1') then 
ser_out<='0';
elsif((clk'event)and(clk='1'))then 
ser_out<=para(4);
end if;
end process;

end behav;