div.vhd

来自「并串转换器：将并行输入的信号以串行方式输出」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity div is
port(--reset:in std_logic;
     signal clk_input:in std_logic;
     signal clk_2:out std_logic;
     signal clk_4:out std_logic;
     signal clk_8:out std_logic);
end div;

architecture behav of div is
signal count:std_logic_vector(2 downto 0);
begin
process(clk_input)
begin
    --if reset='0'then
--system reset,counter set zero--
    --count(2 downto 0)<="000";
    --else
      if(clk_input'event)and(clk_input='1')then
        count(2 downto 0)<=count(2 downto 0)+1;
      else
        null;

      end if;
    --end if;
end process;

clk_2<=count(0);
clk_4<=count(1);
clk_8<=count(2);
end behav;