📄 top.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\counter\top.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+------------------------------- LC81 |CNT2:1|:2
| +----------------------------- LC82 |CNT2:1|:4
| | +--------------------------- LC94 led0
| | | +------------------------- LC93 led1
| | | | +----------------------- LC91 led2
| | | | | +--------------------- LC88 led3
| | | | | | +------------------- LC86 led4
| | | | | | | +----------------- LC85 led5
| | | | | | | | +--------------- LC83 led6
| | | | | | | | | +------------- LC95 |LED7:2|~221~1
| | | | | | | | | | +----------- LC96 |LED7:2|~227~1
| | | | | | | | | | | +--------- LC92 |LED7:2|~233~1
| | | | | | | | | | | | +------- LC90 |LED7:2|~239~1
| | | | | | | | | | | | | +----- LC89 |LED7:2|~245~1
| | | | | | | | | | | | | | +--- LC87 |LED7:2|~251~1
| | | | | | | | | | | | | | | +- LC84 |LED7:2|~257~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC81 -> * - * - * * * * * * * * * * - * | - - - - - * - - | <-- |CNT2:1|:2
LC82 -> * * * - * * * * * * * * * * - * | - - - - - * - - | <-- |CNT2:1|:4
LC95 -> - - - - - - - - * * - - - - - - | - - - - - * - - | <-- |LED7:2|~221~1
LC96 -> - - - - - - - * - - * - - - - - | - - - - - * - - | <-- |LED7:2|~227~1
LC92 -> - - - - - - * - - - - * - - - - | - - - - - * - - | <-- |LED7:2|~233~1
LC90 -> - - - - - * - - - - - - * - - - | - - - - - * - - | <-- |LED7:2|~239~1
LC89 -> - - - - * - - - - - - - - * - - | - - - - - * - - | <-- |LED7:2|~245~1
LC87 -> - - - * - - - - - - - - - - * - | - - - - - * - - | <-- |LED7:2|~251~1
LC84 -> - - * - - - - - - - - - - - - * | - - - - - * - - | <-- |LED7:2|~257~1
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
45 -> - - * * * * * * * * * * * * * * | - - - - - * - - | <-- en
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\counter\top.rpt
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** EQUATIONS **
clk : INPUT;
en : INPUT;
-- Node name is 'led0'
-- Equation name is 'led0', location is LC094, type is output.
led0 = LCELL( _EQ001 $ GND);
_EQ001 = en & _X001 & _X002
# !en & _LC084;
_X001 = EXP(!_LC081 & !_LC082);
_X002 = EXP(!_LC081 & _LC082);
-- Node name is 'led1'
-- Equation name is 'led1', location is LC093, type is output.
led1 = LCELL( _EQ002 $ GND);
_EQ002 = !en & _LC087;
-- Node name is 'led2'
-- Equation name is 'led2', location is LC091, type is output.
led2 = LCELL( _EQ003 $ GND);
_EQ003 = en & _LC081 & !_LC082 & _X001
# !en & _LC089;
_X001 = EXP(!_LC081 & !_LC082);
-- Node name is 'led3'
-- Equation name is 'led3', location is LC088, type is output.
led3 = LCELL( _EQ004 $ GND);
_EQ004 = en & _X001 & _X002
# !en & _LC090;
_X001 = EXP(!_LC081 & !_LC082);
_X002 = EXP(!_LC081 & _LC082);
-- Node name is 'led4'
-- Equation name is 'led4', location is LC086, type is output.
led4 = LCELL( _EQ005 $ GND);
_EQ005 = en & _X001 & _X003
# !en & _LC092;
_X001 = EXP(!_LC081 & !_LC082);
_X003 = EXP( _LC081 & !_LC082);
-- Node name is 'led5'
-- Equation name is 'led5', location is LC085, type is output.
led5 = LCELL( _EQ006 $ GND);
_EQ006 = en & _X001
# !en & _LC096;
_X001 = EXP(!_LC081 & !_LC082);
-- Node name is 'led6'
-- Equation name is 'led6', location is LC083, type is output.
led6 = LCELL( _EQ007 $ GND);
_EQ007 = en & _X002
# !en & _LC095;
_X002 = EXP(!_LC081 & _LC082);
-- Node name is '|CNT2:1|:2'
-- Equation name is '_LC081', type is buried
_LC081 = TFFE( _LC082, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|CNT2:1|:4'
-- Equation name is '_LC082', type is buried
_LC082 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|LED7:2|~221~1'
-- Equation name is '_LC095', type is buried
-- synthesized logic cell
_LC095 = LCELL( _EQ008 $ VCC);
_EQ008 = en & !_LC081 & _LC082
# !en & !_LC095
# !_LC081 & _LC082 & !_LC095;
-- Node name is '|LED7:2|~227~1'
-- Equation name is '_LC096', type is buried
-- synthesized logic cell
_LC096 = LCELL( _EQ009 $ VCC);
_EQ009 = en & !_LC081 & !_LC082
# !en & !_LC096
# !_LC081 & !_LC082 & !_LC096;
-- Node name is '|LED7:2|~233~1'
-- Equation name is '_LC092', type is buried
-- synthesized logic cell
_LC092 = LCELL( _EQ010 $ GND);
_EQ010 = en & _LC082 & _X001
# en & !_LC081 & _X001
# !en & _LC092
# _LC082 & _LC092 & _X001
# !_LC081 & _LC092 & _X001;
_X001 = EXP(!_LC081 & !_LC082);
-- Node name is '|LED7:2|~239~1'
-- Equation name is '_LC090', type is buried
-- synthesized logic cell
_LC090 = LCELL( _EQ011 $ GND);
_EQ011 = en & _LC081 & _X001
# en & !_LC082 & _X001
# !en & _LC090
# _LC081 & _LC090 & _X001
# !_LC082 & _LC090 & _X001;
_X001 = EXP(!_LC081 & !_LC082);
-- Node name is '|LED7:2|~245~1'
-- Equation name is '_LC089', type is buried
-- synthesized logic cell
_LC089 = LCELL( _EQ012 $ GND);
_EQ012 = en & _LC081 & !_LC082 & _X001
# !en & _LC089
# _LC081 & !_LC082 & _LC089 & _X001;
_X001 = EXP(!_LC081 & !_LC082);
-- Node name is '|LED7:2|~251~1'
-- Equation name is '_LC087', type is buried
-- synthesized logic cell
_LC087 = LCELL( _EQ013 $ GND);
_EQ013 = !en & _LC087;
-- Node name is '|LED7:2|~257~1'
-- Equation name is '_LC084', type is buried
-- synthesized logic cell
_LC084 = LCELL( _EQ014 $ GND);
_EQ014 = en & _X001 & _X002
# !en & _LC084
# _LC084 & _X001 & _X002;
_X001 = EXP(!_LC081 & !_LC082);
_X002 = EXP(!_LC081 & _LC082);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\counter\top.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,596K
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