led7.vhd

来自「利用EDA工具MAX-PlusII的VDHL输入法」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;

entity led7 is
  port (a:in std_logic_vector(1 downto 0);
        en:in std_logic;
        led:out std_logic_vector(6 downto 0));
end led7;

architecture state of led7 is
begin
  process(en,a)
    begin
     if(en='1') then
    case a(1 downto 0) is
    when "00"=>led<="1000000";
    when "01"=>led<="0110000";
    when "10"=>led<="1101101";
    when "11"=>led<="1111001";
    when others =>NULL;
    end case;
     end if;
  end process;
end state;