led7.rpt

利用EDA工具MAX-PlusII的VDHL输入法

LC21 -> - - - * - - - - - - * - - - | - * | <-- ~239~1
LC22 -> - - * - - - - - - - - * - - | - * | <-- ~245~1
LC23 -> - * - - - - - - - - - - * - | - * | <-- ~251~1
LC27 -> * - - - - - - - - - - - - * | - * | <-- ~257~1

Pin
4    -> * - * * * * * * * * * * - * | - * | <-- a0
5    -> * - * * * * * * * * * * - * | - * | <-- a1
6    -> * * * * * * * * * * * * * * | - * | <-- en


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\counter\led7.rpt
led7

** EQUATIONS **

a0       : INPUT;
a1       : INPUT;
en       : INPUT;

-- Node name is 'led0' 
-- Equation name is 'led0', location is LC026, type is output.
 led0    = LCELL( _EQ001 $  GND);
  _EQ001 =  en &  _X001 &  _X002
         # !en &  _LC027;
  _X001  = EXP(!a0 & !a1);
  _X002  = EXP( a0 & !a1);

-- Node name is 'led1' 
-- Equation name is 'led1', location is LC029, type is output.
 led1    = LCELL( _EQ002 $  GND);
  _EQ002 = !en &  _LC023;

-- Node name is 'led2' 
-- Equation name is 'led2', location is LC030, type is output.
 led2    = LCELL( _EQ003 $  GND);
  _EQ003 = !a0 &  a1 &  en &  _X001
         # !en &  _LC022;
  _X001  = EXP(!a0 & !a1);

-- Node name is 'led3' 
-- Equation name is 'led3', location is LC028, type is output.
 led3    = LCELL( _EQ004 $  GND);
  _EQ004 =  en &  _X001 &  _X002
         # !en &  _LC021;
  _X001  = EXP(!a0 & !a1);
  _X002  = EXP( a0 & !a1);

-- Node name is 'led4' 
-- Equation name is 'led4', location is LC025, type is output.
 led4    = LCELL( _EQ005 $  GND);
  _EQ005 =  en &  _X001 &  _X003
         # !en &  _LC020;
  _X001  = EXP(!a0 & !a1);
  _X003  = EXP(!a0 &  a1);

-- Node name is 'led5' 
-- Equation name is 'led5', location is LC024, type is output.
 led5    = LCELL( _EQ006 $  GND);
  _EQ006 =  en &  _X001
         # !en &  _LC019;
  _X001  = EXP(!a0 & !a1);

-- Node name is 'led6' 
-- Equation name is 'led6', location is LC017, type is output.
 led6    = LCELL( _EQ007 $  GND);
  _EQ007 =  en &  _X002
         # !en &  _LC018;
  _X002  = EXP( a0 & !a1);

-- Node name is '~221~1' 
-- Equation name is '~221~1', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ008 $  VCC);
  _EQ008 =  a0 & !a1 &  en
         # !en & !_LC018
         #  a0 & !a1 & !_LC018;

-- Node name is '~227~1' 
-- Equation name is '~227~1', location is LC019, type is buried.
-- synthesized logic cell 
_LC019   = LCELL( _EQ009 $  GND);
  _EQ009 =  a0 &  en
         #  a1 &  en
         # !en &  _LC019
         #  a0 &  _LC019
         #  a1 &  _LC019;

-- Node name is '~233~1' 
-- Equation name is '~233~1', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ010 $  GND);
  _EQ010 =  en &  _X001 &  _X003
         # !en &  _LC020
         #  _LC020 &  _X001 &  _X003;
  _X001  = EXP(!a0 & !a1);
  _X003  = EXP(!a0 &  a1);

-- Node name is '~239~1' 
-- Equation name is '~239~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ011 $  GND);
  _EQ011 =  en &  _X001 &  _X002
         # !en &  _LC021
         #  _LC021 &  _X001 &  _X002;
  _X001  = EXP(!a0 & !a1);
  _X002  = EXP( a0 & !a1);

-- Node name is '~245~1' 
-- Equation name is '~245~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ012 $  GND);
  _EQ012 = !a0 &  a1 &  en &  _X001
         # !en &  _LC022
         # !a0 &  a1 &  _LC022 &  _X001;
  _X001  = EXP(!a0 & !a1);

-- Node name is '~251~1' 
-- Equation name is '~251~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ013 $  GND);
  _EQ013 = !en &  _LC023;

-- Node name is '~257~1' 
-- Equation name is '~257~1', location is LC027, type is buried.
-- synthesized logic cell 
_LC027   = LCELL( _EQ014 $  GND);
  _EQ014 =  en &  _X001 &  _X002
         # !en &  _LC027
         #  _LC027 &  _X001 &  _X002;
  _X001  = EXP(!a0 & !a1);
  _X002  = EXP( a0 & !a1);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        e:\counter\led7.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,383K