📄 led7.rpt
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Project Information e:\counter\led7.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 03/21/2006 22:58:07
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
LED7
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
led7 EPM7032LC44-6 3 7 0 14 3 43 %
User Pins: 3 7 0
Device-Specific Information: e:\counter\led7.rpt
led7
***** Logic for device 'led7' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R
E
S
E
l R
V G G G G G e V
e a a C N N N N N d E
n 1 0 C D D D D D 6 D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
RESERVED | 7 39 | RESERVED
RESERVED | 8 38 | RESERVED
RESERVED | 9 37 | RESERVED
GND | 10 36 | RESERVED
RESERVED | 11 35 | VCC
RESERVED | 12 EPM7032LC44-6 34 | RESERVED
RESERVED | 13 33 | led5
RESERVED | 14 32 | led4
VCC | 15 31 | led0
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R l l l
E E E E N C E E e e e
S S S S D C S S d d d
E E E E E E 2 1 3
R R R R R R
V V V V V V
E E E E E E
D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\counter\led7.rpt
led7
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 3/16( 18%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 14/16( 87%) 7/16( 43%) 4/16( 25%) 10/36( 27%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 10/32 ( 31%)
Total logic cells used: 14/32 ( 43%)
Total shareable expanders used: 3/32 ( 9%)
Total Turbo logic cells used: 14/32 ( 43%)
Total shareable expanders not available (n/a): 1/32 ( 3%)
Average fan-in: 3.71
Total fan-in: 52
Total input pins required: 3
Total output pins required: 7
Total bidirectional pins required: 0
Total logic cells required: 14
Total flipflops required: 0
Total product terms required: 37
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 3
Synthesized logic cells: 7/ 32 ( 21%)
Device-Specific Information: e:\counter\led7.rpt
led7
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 6 6 a0
5 (2) (A) INPUT 0 0 0 0 0 6 6 a1
6 (3) (A) INPUT 0 0 0 0 0 7 7 en
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\counter\led7.rpt
led7
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
31 26 B OUTPUT t 2 2 0 3 1 0 0 led0
27 29 B OUTPUT t 0 0 0 1 1 0 0 led1
26 30 B OUTPUT t 1 1 0 3 1 0 0 led2
28 28 B OUTPUT t 2 2 0 3 1 0 0 led3
32 25 B OUTPUT t 2 2 0 3 1 0 0 led4
33 24 B OUTPUT t 1 1 0 3 1 0 0 led5
41 17 B OUTPUT t 1 1 0 3 1 0 0 led6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\counter\led7.rpt
led7
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(40) 18 B LCELL s t 0 0 0 3 1 1 1 ~221~1
(39) 19 B LCELL s t 1 0 1 3 1 1 1 ~227~1
(38) 20 B LCELL s t 2 2 0 3 1 1 1 ~233~1
(37) 21 B LCELL s t 2 2 0 3 1 1 1 ~239~1
(36) 22 B LCELL s t 1 1 0 3 1 1 1 ~245~1
(34) 23 B LCELL s t 0 0 0 1 1 1 1 ~251~1
(29) 27 B LCELL s t 2 2 0 3 1 1 1 ~257~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\counter\led7.rpt
led7
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------------- LC26 led0
| +------------------------- LC29 led1
| | +----------------------- LC30 led2
| | | +--------------------- LC28 led3
| | | | +------------------- LC25 led4
| | | | | +----------------- LC24 led5
| | | | | | +--------------- LC17 led6
| | | | | | | +------------- LC18 ~221~1
| | | | | | | | +----------- LC19 ~227~1
| | | | | | | | | +--------- LC20 ~233~1
| | | | | | | | | | +------- LC21 ~239~1
| | | | | | | | | | | +----- LC22 ~245~1
| | | | | | | | | | | | +--- LC23 ~251~1
| | | | | | | | | | | | | +- LC27 ~257~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC18 -> - - - - - - * * - - - - - - | - * | <-- ~221~1
LC19 -> - - - - - * - - * - - - - - | - * | <-- ~227~1
LC20 -> - - - - * - - - - * - - - - | - * | <-- ~233~1
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