exp9.tan.rpt

来自「四人抢答器」· RPT 代码 · 共 363 行 · 第 1/3 页

; N/A           ; None        ; -7.754 ns ; Y[0] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg2 ; Clk      ;
; N/A           ; None        ; -7.920 ns ; Y[2] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg2 ; Clk      ;
; N/A           ; None        ; -7.929 ns ; X[0] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 ; Clk      ;
; N/A           ; None        ; -7.937 ns ; Y[2] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 ; Clk      ;
; N/A           ; None        ; -7.951 ns ; Y[1] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg2 ; Clk      ;
; N/A           ; None        ; -8.047 ns ; X[3] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 ; Clk      ;
; N/A           ; None        ; -8.116 ns ; X[1] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 ; Clk      ;
; N/A           ; None        ; -8.288 ns ; X[2] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg2 ; Clk      ;
; N/A           ; None        ; -8.294 ns ; X[2] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 ; Clk      ;
; N/A           ; None        ; -8.352 ns ; X[1] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 ; Clk      ;
; N/A           ; None        ; -8.352 ns ; Y[0] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 ; Clk      ;
; N/A           ; None        ; -8.549 ns ; Y[1] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3 ; Clk      ;
; N/A           ; None        ; -8.759 ns ; Y[2] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 ; Clk      ;
; N/A           ; None        ; -8.785 ns ; Y[1] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 ; Clk      ;
; N/A           ; None        ; -8.872 ns ; X[3] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg2 ; Clk      ;
; N/A           ; None        ; -8.921 ns ; Y[2] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 ; Clk      ;
; N/A           ; None        ; -9.055 ns ; X[3] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 ; Clk      ;
; N/A           ; None        ; -9.127 ns ; X[2] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 ; Clk      ;
; N/A           ; None        ; -9.289 ns ; X[2] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1 ; Clk      ;
; N/A           ; None        ; -9.702 ns ; X[3] ; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0 ; Clk      ;
+---------------+-------------+-----------+------+--------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue May 19 08:57:40 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off exp9 -c exp9 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clk" is an undefined clock
Info: Clock "Clk" Internal fmax is restricted to 180.05 MHz between source register "SEG_SEL[0]~reg0" and destination memory "altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1"
    Info: fmax restricted to Clock High delay (2.777 ns) plus Clock Low delay (2.777 ns) : restricted to 5.554 ns. Expand message to see actual delay path.
        Info: + Longest register to memory delay is 5.040 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y1_N19; Fanout = 10; REG Node = 'SEG_SEL[0]~reg0'
            Info: 2: + IC(0.782 ns) + CELL(0.651 ns) = 1.433 ns; Loc. = LCCOMB_X27_Y1_N14; Fanout = 1; COMB Node = 'Disp_Temp[1]~1343'
            Info: 3: + IC(0.599 ns) + CELL(0.651 ns) = 2.683 ns; Loc. = LCCOMB_X27_Y1_N0; Fanout = 1; COMB Node = 'Disp_Temp[1]~1345'
            Info: 4: + IC(1.048 ns) + CELL(0.319 ns) = 4.050 ns; Loc. = LCCOMB_X27_Y1_N16; Fanout = 1; COMB Node = 'Disp_Temp[1]~1347'
            Info: 5: + IC(0.814 ns) + CELL(0.176 ns) = 5.040 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1'
            Info: Total cell delay = 1.797 ns ( 35.65 % )
            Info: Total interconnect delay = 3.243 ns ( 64.35 % )
        Info: - Smallest clock skew is 0.097 ns
            Info: + Shortest clock path from clock "Clk" to destination memory is 3.225 ns
                Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'Clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'Clk~clkctrl'
                Info: 3: + IC(1.151 ns) + CELL(0.835 ns) = 3.225 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1'
                Info: Total cell delay = 1.935 ns ( 60.00 % )
                Info: Total interconnect delay = 1.290 ns ( 40.00 % )
            Info: - Longest clock path from clock "Clk" to source register is 3.128 ns
                Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'Clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'Clk~clkctrl'
                Info: 3: + IC(1.223 ns) + CELL(0.666 ns) = 3.128 ns; Loc. = LCFF_X27_Y1_N19; Fanout = 10; REG Node = 'SEG_SEL[0]~reg0'
                Info: Total cell delay = 1.766 ns ( 56.46 % )
                Info: Total interconnect delay = 1.362 ns ( 43.54 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is 0.046 ns
Info: tsu for memory "altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1" (data pin = "Y[1]", clock pin = "Clk") is 12.825 ns
    Info: + Longest pin to memory delay is 16.004 ns
        Info: 1: + IC(0.000 ns) + CELL(0.904 ns) = 0.904 ns; Loc. = PIN_AA10; Fanout = 2; PIN Node = 'Y[1]'
        Info: 2: + IC(6.977 ns) + CELL(0.651 ns) = 8.532 ns; Loc. = LCCOMB_X25_Y1_N12; Fanout = 5; COMB Node = 'S2~18'
        Info: 3: + IC(0.404 ns) + CELL(0.206 ns) = 9.142 ns; Loc. = LCCOMB_X25_Y1_N0; Fanout = 2; COMB Node = 'S3~68'
        Info: 4: + IC(0.367 ns) + CELL(0.624 ns) = 10.133 ns; Loc. = LCCOMB_X25_Y1_N2; Fanout = 8; COMB Node = 'result~3'
        Info: 5: + IC(0.381 ns) + CELL(0.206 ns) = 10.720 ns; Loc. = LCCOMB_X25_Y1_N20; Fanout = 2; COMB Node = 'Disp_Temp[3]~1353'
        Info: 6: + IC(1.053 ns) + CELL(0.624 ns) = 12.397 ns; Loc. = LCCOMB_X27_Y1_N14; Fanout = 1; COMB Node = 'Disp_Temp[1]~1343'
        Info: 7: + IC(0.599 ns) + CELL(0.651 ns) = 13.647 ns; Loc. = LCCOMB_X27_Y1_N0; Fanout = 1; COMB Node = 'Disp_Temp[1]~1345'
        Info: 8: + IC(1.048 ns) + CELL(0.319 ns) = 15.014 ns; Loc. = LCCOMB_X27_Y1_N16; Fanout = 1; COMB Node = 'Disp_Temp[1]~1347'
        Info: 9: + IC(0.814 ns) + CELL(0.176 ns) = 16.004 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1'
        Info: Total cell delay = 4.361 ns ( 27.25 % )
        Info: Total interconnect delay = 11.643 ns ( 72.75 % )
    Info: + Micro setup delay of destination is 0.046 ns
    Info: - Shortest clock path from clock "Clk" to destination memory is 3.225 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'Clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'Clk~clkctrl'
        Info: 3: + IC(1.151 ns) + CELL(0.835 ns) = 3.225 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg1'
        Info: Total cell delay = 1.935 ns ( 60.00 % )
        Info: Total interconnect delay = 1.290 ns ( 40.00 % )
Info: tco from clock "Clk" to destination pin "Display[3]" through memory "altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0" is 15.681 ns
    Info: + Longest clock path from clock "Clk" to source memory is 3.225 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'Clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'Clk~clkctrl'
        Info: 3: + IC(1.151 ns) + CELL(0.835 ns) = 3.225 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0'
        Info: Total cell delay = 1.935 ns ( 60.00 % )
        Info: Total interconnect delay = 1.290 ns ( 40.00 % )
    Info: + Micro clock to output delay of source is 0.260 ns
    Info: + Longest memory to pin delay is 12.196 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(3.761 ns) = 3.761 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[3]'
        Info: 3: + IC(5.409 ns) + CELL(3.026 ns) = 12.196 ns; Loc. = PIN_L10; Fanout = 0; PIN Node = 'Display[3]'
        Info: Total cell delay = 6.787 ns ( 55.65 % )
        Info: Total interconnect delay = 5.409 ns ( 44.35 % )
Info: Longest tpd from source pin "Y[1]" to destination pin "result[4]" is 17.299 ns
    Info: 1: + IC(0.000 ns) + CELL(0.904 ns) = 0.904 ns; Loc. = PIN_AA10; Fanout = 2; PIN Node = 'Y[1]'
    Info: 2: + IC(6.977 ns) + CELL(0.651 ns) = 8.532 ns; Loc. = LCCOMB_X25_Y1_N12; Fanout = 5; COMB Node = 'S2~18'
    Info: 3: + IC(0.404 ns) + CELL(0.206 ns) = 9.142 ns; Loc. = LCCOMB_X25_Y1_N0; Fanout = 2; COMB Node = 'S3~68'
    Info: 4: + IC(0.373 ns) + CELL(0.624 ns) = 10.139 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 8; COMB Node = 'result~223'
    Info: 5: + IC(3.914 ns) + CELL(3.246 ns) = 17.299 ns; Loc. = PIN_U18; Fanout = 0; PIN Node = 'result[4]'
    Info: Total cell delay = 5.631 ns ( 32.55 % )
    Info: Total interconnect delay = 11.668 ns ( 67.45 % )
Info: th for memory "altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3" (data pin = "Y[3]", clock pin = "Clk") is -5.998 ns
    Info: + Longest clock path from clock "Clk" to destination memory is 3.225 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'Clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'Clk~clkctrl'
        Info: 3: + IC(1.151 ns) + CELL(0.835 ns) = 3.225 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3'
        Info: Total cell delay = 1.935 ns ( 60.00 % )
        Info: Total interconnect delay = 1.290 ns ( 40.00 % )
    Info: + Micro hold delay of destination is 0.267 ns
    Info: - Shortest pin to memory delay is 9.490 ns
        Info: 1: + IC(0.000 ns) + CELL(0.904 ns) = 0.904 ns; Loc. = PIN_AB12; Fanout = 2; PIN Node = 'Y[3]'
        Info: 2: + IC(5.736 ns) + CELL(0.370 ns) = 7.010 ns; Loc. = LCCOMB_X25_Y1_N2; Fanout = 8; COMB Node = 'result~3'
        Info: 3: + IC(1.101 ns) + CELL(0.370 ns) = 8.481 ns; Loc. = LCCOMB_X27_Y1_N10; Fanout = 1; COMB Node = 'Disp_Temp[3]~1352'
        Info: 4: + IC(0.833 ns) + CELL(0.176 ns) = 9.490 ns; Loc. = M4K_X26_Y1; Fanout = 7; MEM Node = 'altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ram_block1a0~porta_address_reg3'
        Info: Total cell delay = 1.820 ns ( 19.18 % )
        Info: Total interconnect delay = 7.670 ns ( 80.82 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue May 19 08:57:40 2009
    Info: Elapsed time: 00:00:01