exp9.map.qmsg

来自「四人抢答器」· QMSG 代码 · 共 50 行 · 第 1/2 页

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Display\[7\]~reg0 data_in GND " "Warning: Reduced register \"Display\[7\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 79 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[5\] " "Warning: LATCH primitive \"SEC1\[5\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[4\] " "Warning: LATCH primitive \"SEC1\[4\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[3\] " "Warning: LATCH primitive \"SEC1\[3\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[2\] " "Warning: LATCH primitive \"SEC1\[2\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[1\] " "Warning: LATCH primitive \"SEC1\[1\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[0\] " "Warning: LATCH primitive \"SEC1\[0\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[7\] " "Warning: LATCH primitive \"SEC1\[7\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[6\] " "Warning: LATCH primitive \"SEC1\[6\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[7\] " "Warning: LATCH primitive \"SEC1\[7\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[6\] " "Warning: LATCH primitive \"SEC1\[6\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[5\] " "Warning: LATCH primitive \"SEC1\[5\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[4\] " "Warning: LATCH primitive \"SEC1\[4\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[3\] " "Warning: LATCH primitive \"SEC1\[3\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[2\] " "Warning: LATCH primitive \"SEC1\[2\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[1\] " "Warning: LATCH primitive \"SEC1\[1\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "SEC1\[0\] " "Warning: LATCH primitive \"SEC1\[0\]\" is permanently enabled" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 51 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently enabled" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "Disp_Decode\[6\]~1785 256 7 " "Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=7) from the following design logic: \"Disp_Decode\[6\]~1785\"" {  } { { "exp9.vhd" "Disp_Decode\[6\]~1785" { Text "D:/work/add/exp9.vhd" 25 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_77l.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_77l.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_77l " "Info: Found entity 1: altsyncram_77l" {  } { { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "result\[5\] GND " "Warning: Pin \"result\[5\]\" stuck at GND" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "result\[6\] GND " "Warning: Pin \"result\[6\]\" stuck at GND" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "result\[7\] GND " "Warning: Pin \"result\[7\]\" stuck at GND" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Display\[7\] GND " "Warning: Pin \"Display\[7\]\" stuck at GND" {  } { { "exp9.vhd" "" { Text "D:/work/add/exp9.vhd" 79 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_REMOVED_CONST_ADDR_LINES" "altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ALTSYNCRAM 4 " "Info: Removed 4 MSB VCC or GND address nodes from RAM block \"altsyncram:Disp_Decode_rtl_0\|altsyncram_77l:auto_generated\|ALTSYNCRAM\"" {  } { { "db/altsyncram_77l.tdf" "" { Text "D:/work/add/db/altsyncram_77l.tdf" 40 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Removed %2!d! MSB VCC or GND address nodes from RAM block \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "63 " "Info: Implemented 63 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "28 " "Info: Implemented 28 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "7 " "Info: Implemented 7 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 42 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 42 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 19 08:57:11 2009 " "Info: Processing ended: Tue May 19 08:57:11 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}