exp9.map.rpt

四人抢答器

; NUMWORDS_A                         ; 256            ; Untyped                 ;
; OUTDATA_REG_A                      ; UNREGISTERED   ; Untyped                 ;
; ADDRESS_ACLR_A                     ; NONE           ; Untyped                 ;
; OUTDATA_ACLR_A                     ; NONE           ; Untyped                 ;
; WRCONTROL_ACLR_A                   ; NONE           ; Untyped                 ;
; INDATA_ACLR_A                      ; NONE           ; Untyped                 ;
; BYTEENA_ACLR_A                     ; NONE           ; Untyped                 ;
; WIDTH_B                            ; 1              ; Untyped                 ;
; WIDTHAD_B                          ; 1              ; Untyped                 ;
; NUMWORDS_B                         ; 1              ; Untyped                 ;
; INDATA_REG_B                       ; CLOCK1         ; Untyped                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1         ; Untyped                 ;
; RDCONTROL_REG_B                    ; CLOCK1         ; Untyped                 ;
; ADDRESS_REG_B                      ; CLOCK1         ; Untyped                 ;
; OUTDATA_REG_B                      ; UNREGISTERED   ; Untyped                 ;
; BYTEENA_REG_B                      ; CLOCK1         ; Untyped                 ;
; INDATA_ACLR_B                      ; NONE           ; Untyped                 ;
; WRCONTROL_ACLR_B                   ; NONE           ; Untyped                 ;
; ADDRESS_ACLR_B                     ; NONE           ; Untyped                 ;
; OUTDATA_ACLR_B                     ; NONE           ; Untyped                 ;
; RDCONTROL_ACLR_B                   ; NONE           ; Untyped                 ;
; BYTEENA_ACLR_B                     ; NONE           ; Untyped                 ;
; WIDTH_BYTEENA_A                    ; 1              ; Untyped                 ;
; WIDTH_BYTEENA_B                    ; 1              ; Untyped                 ;
; RAM_BLOCK_TYPE                     ; AUTO           ; Untyped                 ;
; BYTE_SIZE                          ; 8              ; Untyped                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE      ; Untyped                 ;
; INIT_FILE                          ; exp90.rtl.mif  ; Untyped                 ;
; INIT_FILE_LAYOUT                   ; PORT_A         ; Untyped                 ;
; MAXIMUM_DEPTH                      ; 0              ; Untyped                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL         ; Untyped                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL         ; Untyped                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL         ; Untyped                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL         ; Untyped                 ;
; DEVICE_FAMILY                      ; Cyclone II     ; Untyped                 ;
; CBXI_PARAMETER                     ; altsyncram_77l ; Untyped                 ;
+------------------------------------+----------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/work/add/exp9.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue May 19 08:57:07 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off exp9 -c exp9
Info: Found 2 design units, including 1 entities, in source file exp9.vhd
    Info: Found design unit 1: exp9-behave
    Info: Found entity 1: exp9
Info: Elaborating entity "exp9" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at exp9.vhd(41): signal "S1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(42): signal "S1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(43): signal "S2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(44): signal "S2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(45): signal "S3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(46): signal "S3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(53): signal "m_Result" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(54): signal "m_Result" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(55): signal "m_Result" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(56): signal "m_Result" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(57): signal "result" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(58): signal "m_Result" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(59): signal "m_Result" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(60): signal "m_Result" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at exp9.vhd(51): signal or variable "SEC1" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "SEC1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10631): VHDL Process Statement warning at exp9.vhd(51): signal or variable "SEC10" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "SEC10" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10492): VHDL Process Statement warning at exp9.vhd(68): signal "SEC10" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(69): signal "SEC1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(72): signal "SEC10" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at exp9.vhd(73): signal "SEC1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Reduced register "Display[7]~reg0" with stuck data_in port to stuck value GND
Warning: LATCH primitive "SEC1[5]" is permanently enabled
Warning: LATCH primitive "SEC1[4]" is permanently enabled
Warning: LATCH primitive "SEC1[3]" is permanently enabled
Warning: LATCH primitive "SEC1[2]" is permanently enabled
Warning: LATCH primitive "SEC1[1]" is permanently enabled
Warning: LATCH primitive "SEC1[0]" is permanently enabled
Warning: LATCH primitive "SEC1[7]" is permanently enabled
Warning: LATCH primitive "SEC1[6]" is permanently enabled
Warning: LATCH primitive "SEC1[7]" is permanently enabled
Warning: LATCH primitive "SEC1[6]" is permanently enabled
Warning: LATCH primitive "SEC1[5]" is permanently enabled
Warning: LATCH primitive "SEC1[4]" is permanently enabled
Warning: LATCH primitive "SEC1[3]" is permanently enabled
Warning: LATCH primitive "SEC1[2]" is permanently enabled
Warning: LATCH primitive "SEC1[1]" is permanently enabled
Warning: LATCH primitive "SEC1[0]" is permanently enabled
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=7) from the following design logic: "Disp_Decode[6]~1785"
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_77l.tdf
    Info: Found entity 1: altsyncram_77l
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "result[5]" stuck at GND
    Warning: Pin "result[6]" stuck at GND
    Warning: Pin "result[7]" stuck at GND
    Warning: Pin "Display[7]" stuck at GND
Info: Removed 4 MSB VCC or GND address nodes from RAM block "altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ALTSYNCRAM"
Info: Implemented 63 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 19 output pins
    Info: Implemented 28 logic cells
    Info: Implemented 7 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 42 warnings
    Info: Processing ended: Tue May 19 08:57:11 2009
    Info: Elapsed time: 00:00:05