exp9.map.rpt

四人抢答器

; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                      ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+
; exp9.vhd                         ; yes             ; User VHDL File               ; D:/work/add/exp9.vhd                                              ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Other                        ; e:/altera/quartus51/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Other                        ; e:/altera/quartus51/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Other                        ; e:/altera/quartus51/libraries/megafunctions/lpm_decode.inc        ;
; aglobal51.inc                    ; yes             ; Other                        ; e:/altera/quartus51/libraries/megafunctions/aglobal51.inc         ;
; altsyncram.inc                   ; yes             ; Other                        ; e:/altera/quartus51/libraries/megafunctions/altsyncram.inc        ;
; a_rdenreg.inc                    ; yes             ; Other                        ; e:/altera/quartus51/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Other                        ; e:/altera/quartus51/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Other                        ; e:/altera/quartus51/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Other                        ; e:/altera/quartus51/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Other                        ; e:/altera/quartus51/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_77l.tdf            ; yes             ; Auto-Generated Megafunction  ; D:/work/add/db/altsyncram_77l.tdf                                 ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+


+---------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                   ;
+---------------------------------------------+-----------------+
; Resource                                    ; Usage           ;
+---------------------------------------------+-----------------+
; Total combinational functions               ; 27              ;
; Logic element usage by number of LUT inputs ;                 ;
;     -- 4 input functions                    ; 16              ;
;     -- 3 input functions                    ; 7               ;
;     -- <=2 input functions                  ; 4               ;
;         -- Combinational cells for routing  ; 0               ;
; Logic elements by mode                      ;                 ;
;     -- normal mode                          ; 27              ;
;     -- arithmetic mode                      ; 0               ;
; Total registers                             ; 3               ;
; I/O pins                                    ; 28              ;
; Total memory bits                           ; 112             ;
; Maximum fan-out node                        ; SEG_SEL[0]~reg0 ;
; Maximum fan-out                             ; 10              ;
; Total fan-out                               ; 148             ;
; Average fan-out                             ; 2.28            ;
+---------------------------------------------+-----------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                  ;
+---------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------+
; Compilation Hierarchy Node            ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                              ;
+---------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------+
; |exp9                                 ; 27 (27)           ; 3 (3)        ; 112         ; 0            ; 0       ; 0         ; 28   ; 0            ; |exp9                                                            ;
;    |altsyncram:Disp_Decode_rtl_0|     ; 0 (0)             ; 0 (0)        ; 112         ; 0            ; 0       ; 0         ; 0    ; 0            ; |exp9|altsyncram:Disp_Decode_rtl_0                               ;
;       |altsyncram_77l:auto_generated| ; 0 (0)             ; 0 (0)        ; 112         ; 0            ; 0       ; 0         ; 0    ; 0            ; |exp9|altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated ;
+---------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                       ;
+-----------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+---------------+
; Name                                                                  ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF           ;
+-----------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+---------------+
; altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 256          ; 7            ; --           ; --           ; 1792 ; exp90.rtl.mif ;
+-----------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+---------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; No         ; |exp9|Disp_Temp[6]         ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |exp9|Disp_Temp[4]         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-----------------------------------------------------------------------------------+
; Source assignments for altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated ;
+---------------------------------+--------------------+------+---------------------+
; Assignment                      ; Value              ; from ; to                  ;
+---------------------------------+--------------------+------+---------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                   ;
+---------------------------------+--------------------+------+---------------------+


+-------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: altsyncram:Disp_Decode_rtl_0 ;
+------------------------------------+----------------+-------------------------+
; Parameter Name                     ; Value          ; Type                    ;
+------------------------------------+----------------+-------------------------+
; BYTE_SIZE_BLOCK                    ; 8              ; Untyped                 ;
; AUTO_CARRY_CHAINS                  ; ON             ; AUTO_CARRY              ;
; IGNORE_CARRY_BUFFERS               ; OFF            ; IGNORE_CARRY            ;
; AUTO_CASCADE_CHAINS                ; ON             ; AUTO_CASCADE            ;
; IGNORE_CASCADE_BUFFERS             ; OFF            ; IGNORE_CASCADE          ;
; OPERATION_MODE                     ; ROM            ; Untyped                 ;
; WIDTH_A                            ; 7              ; Untyped                 ;
; WIDTHAD_A                          ; 8              ; Untyped                 ;