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📄 exp9.vho

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1234 
	sclr => GND,
	sload => GND,
	ena => VCC,
	regout => \SEG_SEL[0]~reg0\);

\add~297_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \add~297\ = \SEG_SEL[1]~reg0\ $ \SEG_SEL[0]~reg0\

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0000111111110000")
-- pragma translate_on
PORT MAP (
	pathsel => \add~297_I_pathsel\,
	dataa => VCC,
	datab => VCC,
	datac => \SEG_SEL[1]~reg0\,
	datad => \SEG_SEL[0]~reg0\,
	cin => GND,
	modesel => \add~297_I_modesel\,
	combout => \add~297\);

\SEG_SEL[1]~reg0_I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \Clk~clkctrl\,
	datain => \add~297\,
	sdata => GND,
	aclr => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	regout => \SEG_SEL[1]~reg0\);

\SEG_SEL[2]~15_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \SEG_SEL[2]~15\ = \SEG_SEL[2]~reg0\ $ (\SEG_SEL[1]~reg0\ & \SEG_SEL[0]~reg0\)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0111100001111000")
-- pragma translate_on
PORT MAP (
	pathsel => \SEG_SEL[2]~15_I_pathsel\,
	dataa => \SEG_SEL[1]~reg0\,
	datab => \SEG_SEL[0]~reg0\,
	datac => \SEG_SEL[2]~reg0\,
	datad => VCC,
	cin => GND,
	modesel => \SEG_SEL[2]~15_I_modesel\,
	combout => \SEG_SEL[2]~15\);

\SEG_SEL[2]~reg0_I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \Clk~clkctrl\,
	datain => \SEG_SEL[2]~15\,
	sdata => GND,
	aclr => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	regout => \SEG_SEL[2]~reg0\);

\Disp_Temp[0]~1341_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[0]~1341\ = \SEG_SEL[0]~reg0\ & \Disp_Temp[0]~1340\ & !\SEG_SEL[1]~reg0\ # !\SEG_SEL[0]~reg0\ & (\result~0\ # !\SEG_SEL[1]~reg0\)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0011101100001011")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[0]~1341_I_pathsel\,
	dataa => \Disp_Temp[0]~1340\,
	datab => \SEG_SEL[0]~reg0\,
	datac => \SEG_SEL[1]~reg0\,
	datad => \result~0\,
	cin => GND,
	modesel => \Disp_Temp[0]~1341_I_modesel\,
	combout => \Disp_Temp[0]~1341\);

\LessThan~581_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \LessThan~581\ = !\result~222\ & !\result~221\ # !\result~3\

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0011001100111111")
-- pragma translate_on
PORT MAP (
	pathsel => \LessThan~581_I_pathsel\,
	dataa => VCC,
	datab => \result~3\,
	datac => \result~222\,
	datad => \result~221\,
	cin => GND,
	modesel => \LessThan~581_I_modesel\,
	combout => \LessThan~581\);

\Disp_Temp[1]~1346_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[1]~1346\ = !\Disp_Temp[0]~1342\ & !\SEG_SEL[0]~reg0\ & (\result~223\ # !\LessThan~581\)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0001000000010001")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[1]~1346_I_pathsel\,
	dataa => \Disp_Temp[0]~1342\,
	datab => \SEG_SEL[0]~reg0\,
	datac => \result~223\,
	datad => \LessThan~581\,
	cin => GND,
	modesel => \Disp_Temp[1]~1346_I_modesel\,
	combout => \Disp_Temp[1]~1346\);

\Disp_Temp[0]~1342_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[0]~1342\ = \result~223\ & (\result~222\ # \result~3\)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1100110010001000")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[0]~1342_I_pathsel\,
	dataa => \result~222\,
	datab => \result~223\,
	datac => VCC,
	datad => \result~3\,
	cin => GND,
	modesel => \Disp_Temp[0]~1342_I_modesel\,
	combout => \Disp_Temp[0]~1342\);

\Disp_Temp[1]~1344_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[1]~1344\ = !\SEG_SEL[0]~reg0\ & !\result~223\ & \LessThan~581\

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0000001100000000")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[1]~1344_I_pathsel\,
	dataa => VCC,
	datab => \SEG_SEL[0]~reg0\,
	datac => \result~223\,
	datad => \LessThan~581\,
	cin => GND,
	modesel => \Disp_Temp[1]~1344_I_modesel\,
	combout => \Disp_Temp[1]~1344\);

\Disp_Temp[1]~1345_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[1]~1345\ = \Disp_Temp[1]~1343\ & (\Disp_Temp[0]~1342\ # \result~221\ & \Disp_Temp[1]~1344\) # !\Disp_Temp[1]~1343\ & \result~221\ & (\Disp_Temp[1]~1344\)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1110110010100000")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[1]~1345_I_pathsel\,
	dataa => \Disp_Temp[1]~1343\,
	datab => \result~221\,
	datac => \Disp_Temp[0]~1342\,
	datad => \Disp_Temp[1]~1344\,
	cin => GND,
	modesel => \Disp_Temp[1]~1345_I_modesel\,
	combout => \Disp_Temp[1]~1345\);

\Disp_Temp[1]~1347_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[1]~1347\ = \Disp_Temp[1]~1345\ # \Disp_Temp[1]~1346\ & !\result~221\ # !\add~297\

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1111010111111101")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[1]~1347_I_pathsel\,
	dataa => \add~297\,
	datab => \Disp_Temp[1]~1346\,
	datac => \Disp_Temp[1]~1345\,
	datad => \result~221\,
	cin => GND,
	modesel => \Disp_Temp[1]~1347_I_modesel\,
	combout => \Disp_Temp[1]~1347\);

\Disp_Temp[2]~1348_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[2]~1348\ = \result~223\ & !\result~222\ & (\result~3\ # !\result~221\) # !\result~223\ & \result~222\ & (\result~221\ # !\result~3\)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0101100000011010")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[2]~1348_I_pathsel\,
	dataa => \result~223\,
	datab => \result~3\,
	datac => \result~222\,
	datad => \result~221\,
	cin => GND,
	modesel => \Disp_Temp[2]~1348_I_modesel\,
	combout => \Disp_Temp[2]~1348\);

\Disp_Temp[2]~1349_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[2]~1349\ = \SEG_SEL[1]~reg0\ & !\SEG_SEL[0]~reg0\ & \Disp_Temp[2]~1348\

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0010001000000000")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[2]~1349_I_pathsel\,
	dataa => \SEG_SEL[1]~reg0\,
	datab => \SEG_SEL[0]~reg0\,
	datac => VCC,
	datad => \Disp_Temp[2]~1348\,
	cin => GND,
	modesel => \Disp_Temp[2]~1349_I_modesel\,
	combout => \Disp_Temp[2]~1349\);

\Disp_Temp[3]~1353_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[3]~1353\ = \result~3\ & (\S2~18\ $ \Y[2]~combout\ $ \X[2]~combout\)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1001011000000000")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[3]~1353_I_pathsel\,
	dataa => \S2~18\,
	datab => \Y[2]~combout\,
	datac => \X[2]~combout\,
	datad => \result~3\,
	cin => GND,
	modesel => \Disp_Temp[3]~1353_I_modesel\,
	combout => \Disp_Temp[3]~1353\);

\Disp_Temp[3]~1350_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[3]~1350\ = !\SEG_SEL[0]~reg0\ & \Disp_Temp[3]~1353\ & \result~223\ & !\result~221\

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "0000000001000000")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[3]~1350_I_pathsel\,
	dataa => \SEG_SEL[0]~reg0\,
	datab => \Disp_Temp[3]~1353\,
	datac => \result~223\,
	datad => \result~221\,
	cin => GND,
	modesel => \Disp_Temp[3]~1350_I_modesel\,
	combout => \Disp_Temp[3]~1350\);

\Disp_Temp[3]~1351_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[3]~1351\ = \Disp_Temp[3]~1350\ # \Disp_Temp[1]~1344\ & \result~3\ # !\add~297\

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1110110011111111")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[3]~1351_I_pathsel\,
	dataa => \Disp_Temp[1]~1344\,
	datab => \Disp_Temp[3]~1350\,
	datac => \result~3\,
	datad => \add~297\,
	cin => GND,
	modesel => \Disp_Temp[3]~1351_I_modesel\,
	combout => \Disp_Temp[3]~1351\);

\Disp_Temp[3]~1352_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[3]~1352\ = \Disp_Temp[3]~1351\ # \Disp_Temp[1]~1346\ & (\LessThan~582\ $ \result~3\)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1101111011001100")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[3]~1352_I_pathsel\,
	dataa => \LessThan~582\,
	datab => \Disp_Temp[3]~1351\,
	datac => \result~3\,
	datad => \Disp_Temp[1]~1346\,
	cin => GND,
	modesel => \Disp_Temp[3]~1352_I_modesel\,
	combout => \Disp_Temp[3]~1352\);

\Disp_Decode_rtl_0|auto_generated|q_a[0]~I\ : cycloneii_ram_block
-- pragma translate_off
-- GENERIC MAP (
--	mem_init0 => X"00000002827DFFE17EDB3F3B587E",
--	operation_mode => "rom",
--	ram_block_type => "M4K",
--	logical_ram_name => "altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|ALTSYNCRAM",
--	init_file => "exp90.rtl.mif",
--	init_file_layout => "port_a",
--	data_interleave_width_in_bits => 1,
--	data_interleave_offset_in_bits => 1,
--	port_a_write_enable_clock => "none",
--	port_a_byte_enable_clock => "none",
--	port_a_logical_ram_depth => 256,
--	port_a_logical_ram_width => 7,
--	port_a_data_in_clear => "none",
--	port_a_address_clear => "none",
--	port_a_write_enable_clear => "none",
--	port_a_byte_enable_clear => "none",
--	port_a_data_out_clock => "none",
--	port_a_data_out_clear => "none",
--	port_a_first_address => 0,
--	port_a_last_address => 15,
--	port_a_first_bit_number => 0,
--	port_a_data_width => 7,
--	port_a_address_width => 4,
--	port_b_address_width => 4,
--	port_b_data_width => 7,
--	safe_write => "err_on_2clk")
-- pragma translate_on
PORT MAP (
	portawe => GND,
	portaaddrstall => GND,
	portbrewe => GND,
	portbaddrstall => GND,
	clk0 => \Clk~clkctrl\,
	clk1 => GND,
	ena0 => VCC,
	ena1 => VCC,
	clr0 => GND,
	clr1 => GND,
	portadatain => GNDs(143 DOWNTO 0),
	portaaddr => \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTAADDR_bus\,
	portabyteenamasks => GNDs(15 DOWNTO 0),
	portbdatain => GNDs(71 DOWNTO 0),
	portbaddr => GNDs(15 DOWNTO 0),
	portbbyteenamasks => GNDs(15 DOWNTO 0),
	modesel => \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_modesel\,
	portadataout => \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTADATAOUT_bus\);

\result[0]~I\ : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \result~0\,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => \result[0]~I_modesel\,
	padio => ww_result(0));

\result[1]~I\ : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \result~221\,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => \result[1]~I_modesel\,
	padio => ww_result(1));

\result[2]~I\ : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \result~222\,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	differentialin => GND,
	linkin => GND,
	modesel => \result[2]~I_modesel\,
	padio => ww_result(2));

\result[3]~I\ : cycloneii_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \result~3\,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
1234

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