exp9.vho

四人抢答器

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "05/19/2009 08:57:44"

-- 
-- Device: Altera EP2C35F672C8 Package FBGA672
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	exp9 IS
    PORT (
	X : IN std_logic_vector(3 DOWNTO 0);
	Y : IN std_logic_vector(3 DOWNTO 0);
	Clk : IN std_logic;
	result : OUT std_logic_vector(7 DOWNTO 0);
	SEG_SEL : OUT std_logic_vector(2 DOWNTO 0);
	Display : OUT std_logic_vector(7 DOWNTO 0)
	);
END exp9;

ARCHITECTURE structure OF exp9 IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_X : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_Y : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_Clk : std_logic;
SIGNAL ww_result : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_SEG_SEL : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_Display : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTAADDR_bus\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTADATAOUT_bus\ : std_logic_vector(143 DOWNTO 0);
SIGNAL \Clk~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[0]~1340_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[0]~1340_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[1]~1343_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[1]~1343_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan~582_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan~582_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Y[0]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \X[0]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \result~0_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \result~0_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Y[1]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \X[1]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \result~221_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \result~221_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Y[2]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \X[2]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \S2~18_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \S2~18_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \result~222_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \result~222_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \X[3]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \S3~68_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \S3~68_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Y[3]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \S3~67_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \S3~67_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \result~3_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \result~3_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \result~223_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \result~223_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Clk~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Clk~clkctrl_I_modesel\ : std_logic;
SIGNAL \SEG_SEL[0]~16_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \SEG_SEL[0]~16_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \add~297_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \add~297_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \SEG_SEL[2]~15_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \SEG_SEL[2]~15_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[0]~1341_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[0]~1341_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \LessThan~581_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \LessThan~581_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[1]~1346_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[1]~1346_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[0]~1342_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[0]~1342_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[1]~1344_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[1]~1344_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[1]~1345_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[1]~1345_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[1]~1347_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[1]~1347_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[2]~1348_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[2]~1348_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[2]~1349_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[2]~1349_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[3]~1353_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[3]~1353_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[3]~1350_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[3]~1350_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[3]~1351_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[3]~1351_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Temp[3]~1352_I_modesel\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[3]~1352_I_pathsel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_modesel\ : std_logic_vector(48 DOWNTO 0);
SIGNAL \result[0]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \result[1]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \result[2]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \result[3]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \result[4]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \result[5]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \result[6]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \result[7]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \SEG_SEL[0]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \SEG_SEL[1]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \SEG_SEL[2]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Display[0]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Display[1]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Display[2]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Display[3]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Display[4]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Display[5]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Display[6]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Display[7]~I_modesel\ : std_logic_vector(25 DOWNTO 0);
SIGNAL \Disp_Temp[0]~1340\ : std_logic;
SIGNAL \Disp_Temp[1]~1343\ : std_logic;
SIGNAL \LessThan~582\ : std_logic;
SIGNAL \Y[0]~combout\ : std_logic;
SIGNAL \X[0]~combout\ : std_logic;
SIGNAL \result~0\ : std_logic;
SIGNAL \Y[1]~combout\ : std_logic;
SIGNAL \X[1]~combout\ : std_logic;
SIGNAL \result~221\ : std_logic;
SIGNAL \Y[2]~combout\ : std_logic;
SIGNAL \X[2]~combout\ : std_logic;
SIGNAL \S2~18\ : std_logic;
SIGNAL \result~222\ : std_logic;
SIGNAL \X[3]~combout\ : std_logic;
SIGNAL \S3~68\ : std_logic;
SIGNAL \Y[3]~combout\ : std_logic;
SIGNAL \S3~67\ : std_logic;
SIGNAL \result~3\ : std_logic;
SIGNAL \result~223\ : std_logic;
SIGNAL \Clk~combout\ : std_logic;
SIGNAL \Clk~clkctrl\ : std_logic;
SIGNAL \SEG_SEL[0]~16\ : std_logic;
SIGNAL \SEG_SEL[0]~reg0\ : std_logic;
SIGNAL \add~297\ : std_logic;
SIGNAL \SEG_SEL[1]~reg0\ : std_logic;
SIGNAL \SEG_SEL[2]~15\ : std_logic;
SIGNAL \SEG_SEL[2]~reg0\ : std_logic;
SIGNAL \Disp_Temp[0]~1341\ : std_logic;
SIGNAL \LessThan~581\ : std_logic;
SIGNAL \Disp_Temp[1]~1346\ : std_logic;
SIGNAL \Disp_Temp[0]~1342\ : std_logic;
SIGNAL \Disp_Temp[1]~1344\ : std_logic;
SIGNAL \Disp_Temp[1]~1345\ : std_logic;
SIGNAL \Disp_Temp[1]~1347\ : std_logic;
SIGNAL \Disp_Temp[2]~1348\ : std_logic;
SIGNAL \Disp_Temp[2]~1349\ : std_logic;
SIGNAL \Disp_Temp[3]~1353\ : std_logic;
SIGNAL \Disp_Temp[3]~1350\ : std_logic;
SIGNAL \Disp_Temp[3]~1351\ : std_logic;
SIGNAL \Disp_Temp[3]~1352\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[6]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[5]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[4]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[3]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[2]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[1]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[0]\ : std_logic;
COMPONENT cycloneii_lcell_comb
PORT (
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;

COMPONENT cycloneii_lcell_ff
PORT (
	clk : IN STD_LOGIC;
	datain : IN STD_LOGIC;
	sdata : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	regout : OUT STD_LOGIC);
END COMPONENT;

COMPONENT cycloneii_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	differentialin : IN STD_LOGIC;
	linkin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	differentialout : OUT STD_LOGIC;
	linkout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(25 DOWNTO 0));
END COMPONENT;

COMPONENT cycloneii_clkctrl
PORT (
	ena : IN STD_LOGIC;
	inclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	clkselect : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	outclk : OUT STD_LOGIC;
	modesel : IN STD_LOGIC);
END COMPONENT;

COMPONENT cycloneii_ram_block
PORT (
	portawe : IN STD_LOGIC;
	portaaddrstall : IN STD_LOGIC;
	portbrewe : IN STD_LOGIC;
	portbaddrstall : IN STD_LOGIC;
	clk0 : IN STD_LOGIC;
	clk1 : IN STD_LOGIC;
	ena0 : IN STD_LOGIC;
	ena1 : IN STD_LOGIC;
	clr0 : IN STD_LOGIC;
	clr1 : IN STD_LOGIC;
	portadatain : IN STD_LOGIC_VECTOR(143 DOWNTO 0);
	portaaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	portabyteenamasks : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	portbdatain : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
	portbaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	portbbyteenamasks : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	portadataout : OUT STD_LOGIC_VECTOR(143 DOWNTO 0);
	portbdataout : OUT STD_LOGIC_VECTOR(143 DOWNTO 0);
	modesel : IN STD_LOGIC_VECTOR(48 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_X <= X;
ww_Y <= Y;
ww_Clk <= Clk;
result <= ww_result;
SEG_SEL <= ww_SEG_SEL;
Display <= ww_Display;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\Disp_Temp[0]~1340_I_modesel\ <= "1001";
\Disp_Temp[0]~1340_I_pathsel\ <= "00001111";
\Disp_Temp[1]~1343_I_modesel\ <= "1001";
\Disp_Temp[1]~1343_I_pathsel\ <= "00001111";
\LessThan~582_I_modesel\ <= "1001";
\LessThan~582_I_pathsel\ <= "00001111";
\Y[0]~I_modesel\ <= "00000000000000000000000001";
\X[0]~I_modesel\ <= "00000000000000000000000001";
\result~0_I_modesel\ <= "1001";
\result~0_I_pathsel\ <= "00001010";
\Y[1]~I_modesel\ <= "00000000000000000000000001";
\X[1]~I_modesel\ <= "00000000000000000000000001";
\result~221_I_modesel\ <= "1001";
\result~221_I_pathsel\ <= "00001111";
\Y[2]~I_modesel\ <= "00000000000000000000000001";
\X[2]~I_modesel\ <= "00000000000000000000000001";
\S2~18_I_modesel\ <= "1001";
\S2~18_I_pathsel\ <= "00001111";
\result~222_I_modesel\ <= "1001";
\result~222_I_pathsel\ <= "00001110";
\X[3]~I_modesel\ <= "00000000000000000000000001";
\S3~68_I_modesel\ <= "1001";
\S3~68_I_pathsel\ <= "00001100";
\Y[3]~I_modesel\ <= "00000000000000000000000001";
\S3~67_I_modesel\ <= "1001";
\S3~67_I_pathsel\ <= "00001110";
\result~3_I_modesel\ <= "1001";
\result~3_I_pathsel\ <= "00001111";
\result~223_I_modesel\ <= "1001";
\result~223_I_pathsel\ <= "00001111";
\Clk~I_modesel\ <= "00000000000000000000000001";
\Clk~clkctrl_I_modesel\ <= '0';
\SEG_SEL[0]~16_I_modesel\ <= "1001";
\SEG_SEL[0]~16_I_pathsel\ <= "00000100";
\add~297_I_modesel\ <= "1001";
\add~297_I_pathsel\ <= "00001100";
\SEG_SEL[2]~15_I_modesel\ <= "1001";
\SEG_SEL[2]~15_I_pathsel\ <= "00000111";
\Disp_Temp[0]~1341_I_modesel\ <= "1001";
\Disp_Temp[0]~1341_I_pathsel\ <= "00001111";
\LessThan~581_I_modesel\ <= "1001";
\LessThan~581_I_pathsel\ <= "00001110";
\Disp_Temp[1]~1346_I_modesel\ <= "1001";
\Disp_Temp[1]~1346_I_pathsel\ <= "00001111";
\Disp_Temp[0]~1342_I_modesel\ <= "1001";
\Disp_Temp[0]~1342_I_pathsel\ <= "00001011";
\Disp_Temp[1]~1344_I_modesel\ <= "1001";
\Disp_Temp[1]~1344_I_pathsel\ <= "00001110";
\Disp_Temp[1]~1345_I_modesel\ <= "1001";
\Disp_Temp[1]~1345_I_pathsel\ <= "00001111";
\Disp_Temp[1]~1347_I_modesel\ <= "1001";
\Disp_Temp[1]~1347_I_pathsel\ <= "00001111";
\Disp_Temp[2]~1348_I_modesel\ <= "1001";
\Disp_Temp[2]~1348_I_pathsel\ <= "00001111";
\Disp_Temp[2]~1349_I_modesel\ <= "1001";
\Disp_Temp[2]~1349_I_pathsel\ <= "00001011";
\Disp_Temp[3]~1353_I_modesel\ <= "1001";
\Disp_Temp[3]~1353_I_pathsel\ <= "00001111";
\Disp_Temp[3]~1350_I_modesel\ <= "1001";
\Disp_Temp[3]~1350_I_pathsel\ <= "00001111";
\Disp_Temp[3]~1351_I_modesel\ <= "1001";
\Disp_Temp[3]~1351_I_pathsel\ <= "00001111";
\Disp_Temp[3]~1352_I_modesel\ <= "1001";
\Disp_Temp[3]~1352_I_pathsel\ <= "00001111";
\Disp_Decode_rtl_0|auto_generated|q_a[0]~I_modesel\ <= "0000000100000100000000000000000000000000000001000";
\result[0]~I_modesel\ <= "00000000000000000000000010";
\result[1]~I_modesel\ <= "00000000000000000000000010";
\result[2]~I_modesel\ <= "00000000000000000000000010";
\result[3]~I_modesel\ <= "00000000000000000000000010";
\result[4]~I_modesel\ <= "00000000000000000000000010";
\result[5]~I_modesel\ <= "00000000000000000000000010";
\result[6]~I_modesel\ <= "00000000000000000000000010";
\result[7]~I_modesel\ <= "00000000000000000000000010";
\SEG_SEL[0]~I_modesel\ <= "00000000000000000000000010";
\SEG_SEL[1]~I_modesel\ <= "00000000000000000000000010";
\SEG_SEL[2]~I_modesel\ <= "00000000000000000000000010";
\Display[0]~I_modesel\ <= "00000000000000000000000010";
\Display[1]~I_modesel\ <= "00000000000000000000000010";
\Display[2]~I_modesel\ <= "00000000000000000000000010";
\Display[3]~I_modesel\ <= "00000000000000000000000010";
\Display[4]~I_modesel\ <= "00000000000000000000000010";
\Display[5]~I_modesel\ <= "00000000000000000000000010";
\Display[6]~I_modesel\ <= "00000000000000000000000010";
\Display[7]~I_modesel\ <= "00000000000000000000000010";

\Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTAADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \Disp_Temp[3]~1352\ & \Disp_Temp[2]~1349\ & \Disp_Temp[1]~1347\ & \Disp_Temp[0]~1341\);

\Disp_Decode_rtl_0|auto_generated|q_a[0]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTADATAOUT_bus\(0),
	 Y => \Disp_Decode_rtl_0|auto_generated|q_a[0]\);

\Disp_Decode_rtl_0|auto_generated|q_a[1]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTADATAOUT_bus\(1),
	 Y => \Disp_Decode_rtl_0|auto_generated|q_a[1]\);

\Disp_Decode_rtl_0|auto_generated|q_a[2]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTADATAOUT_bus\(2),
	 Y => \Disp_Decode_rtl_0|auto_generated|q_a[2]\);

\Disp_Decode_rtl_0|auto_generated|q_a[3]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTADATAOUT_bus\(3),
	 Y => \Disp_Decode_rtl_0|auto_generated|q_a[3]\);

\Disp_Decode_rtl_0|auto_generated|q_a[4]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTADATAOUT_bus\(4),
	 Y => \Disp_Decode_rtl_0|auto_generated|q_a[4]\);

\Disp_Decode_rtl_0|auto_generated|q_a[5]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTADATAOUT_bus\(5),
	 Y => \Disp_Decode_rtl_0|auto_generated|q_a[5]\);

\Disp_Decode_rtl_0|auto_generated|q_a[6]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \Disp_Decode_rtl_0|auto_generated|q_a[0]~I_PORTADATAOUT_bus\(6),
	 Y => \Disp_Decode_rtl_0|auto_generated|q_a[6]\);


\Clk~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \Clk~combout\);

lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
	 IN1 => GND,
	 Y => lcell_ff_enable_asynch_arcs_out);

\Disp_Temp[0]~1340_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[0]~1340\ = \result~223\ & (\result~3\ & \result~222\ & \result~221\ # !\result~3\ & !\result~222\) # !\result~223\ & \result~3\ & (\result~222\ # \result~221\)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1100011001000010")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[0]~1340_I_pathsel\,
	dataa => \result~223\,
	datab => \result~3\,
	datac => \result~222\,
	datad => \result~221\,
	cin => GND,
	modesel => \Disp_Temp[0]~1340_I_modesel\,
	combout => \Disp_Temp[0]~1340\);

\Disp_Temp[1]~1343_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[1]~1343\ = \SEG_SEL[0]~reg0\ # \result~221\ & (!\result~223\ # !\Disp_Temp[3]~1353\)

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1011111110101010")
-- pragma translate_on
PORT MAP (
	pathsel => \Disp_Temp[1]~1343_I_pathsel\,
	dataa => \SEG_SEL[0]~reg0\,
	datab => \Disp_Temp[3]~1353\,
	datac => \result~223\,
	datad => \result~221\,
	cin => GND,
	modesel => \Disp_Temp[1]~1343_I_modesel\,
	combout => \Disp_Temp[1]~1343\);

\LessThan~582_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \LessThan~582\ = \result~221\ # \S2~18\ $ \Y[2]~combout\ $ \X[2]~combout\

-- pragma translate_off
-- GENERIC MAP (
--	sum_lutc_input => "datac",
--	lut_mask => "1111111110010110")
-- pragma translate_on
PORT MAP (
	pathsel => \LessThan~582_I_pathsel\,
	dataa => \S2~18\,
	datab => \Y[2]~combout\,
	datac => \X[2]~combout\,
	datad => \result~221\,
	cin => GND,
	modesel => \LessThan~582_I_modesel\,
	combout => \LessThan~582\);