exp9.vho

四人抢答器

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "05/19/2009 08:57:44"

-- 
-- Device: Altera EP2C35F672C8 Package FBGA672
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	exp9 IS
    PORT (
	X : IN std_logic_vector(3 DOWNTO 0);
	Y : IN std_logic_vector(3 DOWNTO 0);
	Clk : IN std_logic;
	result : OUT std_logic_vector(7 DOWNTO 0);
	SEG_SEL : OUT std_logic_vector(2 DOWNTO 0);
	Display : OUT std_logic_vector(7 DOWNTO 0)
	);
END exp9;

ARCHITECTURE structure OF exp9 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_X : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_Y : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_Clk : std_logic;
SIGNAL ww_result : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_SEG_SEL : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_Display : std_logic_vector(7 DOWNTO 0);
SIGNAL \Disp_Decode_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Decode_rtl_0|auto_generated|ram_block1a0_PORTADATAOUT_bus\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Clk~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \Disp_Temp[0]~1340\ : std_logic;
SIGNAL \Disp_Temp[1]~1343\ : std_logic;
SIGNAL \LessThan~582\ : std_logic;
SIGNAL \Y[0]~combout\ : std_logic;
SIGNAL \X[0]~combout\ : std_logic;
SIGNAL \result~0\ : std_logic;
SIGNAL \Y[1]~combout\ : std_logic;
SIGNAL \X[1]~combout\ : std_logic;
SIGNAL \result~221\ : std_logic;
SIGNAL \Y[2]~combout\ : std_logic;
SIGNAL \X[2]~combout\ : std_logic;
SIGNAL \S2~18\ : std_logic;
SIGNAL \result~222\ : std_logic;
SIGNAL \X[3]~combout\ : std_logic;
SIGNAL \S3~68\ : std_logic;
SIGNAL \Y[3]~combout\ : std_logic;
SIGNAL \S3~67\ : std_logic;
SIGNAL \result~3\ : std_logic;
SIGNAL \result~223\ : std_logic;
SIGNAL \Clk~combout\ : std_logic;
SIGNAL \Clk~clkctrl\ : std_logic;
SIGNAL \SEG_SEL[0]~16\ : std_logic;
SIGNAL \SEG_SEL[0]~reg0\ : std_logic;
SIGNAL \add~297\ : std_logic;
SIGNAL \SEG_SEL[1]~reg0\ : std_logic;
SIGNAL \SEG_SEL[2]~15\ : std_logic;
SIGNAL \SEG_SEL[2]~reg0\ : std_logic;
SIGNAL \Disp_Temp[0]~1341\ : std_logic;
SIGNAL \LessThan~581\ : std_logic;
SIGNAL \Disp_Temp[1]~1346\ : std_logic;
SIGNAL \Disp_Temp[0]~1342\ : std_logic;
SIGNAL \Disp_Temp[1]~1344\ : std_logic;
SIGNAL \Disp_Temp[1]~1345\ : std_logic;
SIGNAL \Disp_Temp[1]~1347\ : std_logic;
SIGNAL \Disp_Temp[2]~1348\ : std_logic;
SIGNAL \Disp_Temp[2]~1349\ : std_logic;
SIGNAL \Disp_Temp[3]~1353\ : std_logic;
SIGNAL \Disp_Temp[3]~1350\ : std_logic;
SIGNAL \Disp_Temp[3]~1351\ : std_logic;
SIGNAL \Disp_Temp[3]~1352\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[6]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[5]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[4]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[3]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[2]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[1]\ : std_logic;
SIGNAL \Disp_Decode_rtl_0|auto_generated|q_a[0]\ : std_logic;

BEGIN

ww_X <= X;
ww_Y <= Y;
ww_Clk <= Clk;
result <= ww_result;
SEG_SEL <= ww_SEG_SEL;
Display <= ww_Display;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\Disp_Decode_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\Disp_Temp[3]~1352\ & \Disp_Temp[2]~1349\ & \Disp_Temp[1]~1347\ & \Disp_Temp[0]~1341\);

\Disp_Decode_rtl_0|auto_generated|q_a[0]\ <= \Disp_Decode_rtl_0|auto_generated|ram_block1a0_PORTADATAOUT_bus\(0);
\Disp_Decode_rtl_0|auto_generated|q_a[1]\ <= \Disp_Decode_rtl_0|auto_generated|ram_block1a0_PORTADATAOUT_bus\(1);
\Disp_Decode_rtl_0|auto_generated|q_a[2]\ <= \Disp_Decode_rtl_0|auto_generated|ram_block1a0_PORTADATAOUT_bus\(2);
\Disp_Decode_rtl_0|auto_generated|q_a[3]\ <= \Disp_Decode_rtl_0|auto_generated|ram_block1a0_PORTADATAOUT_bus\(3);
\Disp_Decode_rtl_0|auto_generated|q_a[4]\ <= \Disp_Decode_rtl_0|auto_generated|ram_block1a0_PORTADATAOUT_bus\(4);
\Disp_Decode_rtl_0|auto_generated|q_a[5]\ <= \Disp_Decode_rtl_0|auto_generated|ram_block1a0_PORTADATAOUT_bus\(5);
\Disp_Decode_rtl_0|auto_generated|q_a[6]\ <= \Disp_Decode_rtl_0|auto_generated|ram_block1a0_PORTADATAOUT_bus\(6);

\Clk~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \Clk~combout\);

\Disp_Temp[0]~1340_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[0]~1340\ = \result~223\ & (\result~3\ & \result~222\ & \result~221\ # !\result~3\ & !\result~222\) # !\result~223\ & \result~3\ & (\result~222\ # \result~221\)

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "1100011001000010")
-- pragma translate_on
PORT MAP (
	dataa => \result~223\,
	datab => \result~3\,
	datac => \result~222\,
	datad => \result~221\,
	combout => \Disp_Temp[0]~1340\);

\Disp_Temp[1]~1343_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \Disp_Temp[1]~1343\ = \SEG_SEL[0]~reg0\ # \result~221\ & (!\result~223\ # !\Disp_Temp[3]~1353\)

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "1011111110101010")
-- pragma translate_on
PORT MAP (
	dataa => \SEG_SEL[0]~reg0\,
	datab => \Disp_Temp[3]~1353\,
	datac => \result~223\,
	datad => \result~221\,
	combout => \Disp_Temp[1]~1343\);

\LessThan~582_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \LessThan~582\ = \result~221\ # \S2~18\ $ \Y[2]~combout\ $ \X[2]~combout\

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "1111111110010110")
-- pragma translate_on
PORT MAP (
	dataa => \S2~18\,
	datab => \Y[2]~combout\,
	datac => \X[2]~combout\,
	datad => \result~221\,
	combout => \LessThan~582\);

\Y[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_Y(0),
	combout => \Y[0]~combout\);

\X[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_X(0),
	combout => \X[0]~combout\);

\result~0_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \result~0\ = \Y[0]~combout\ $ \X[0]~combout\

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "0011001111001100")
-- pragma translate_on
PORT MAP (
	datab => \Y[0]~combout\,
	datad => \X[0]~combout\,
	combout => \result~0\);

\Y[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_Y(1),
	combout => \Y[1]~combout\);

\X[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_X(1),
	combout => \X[1]~combout\);

\result~221_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \result~221\ = \Y[1]~combout\ $ \X[1]~combout\ $ (\Y[0]~combout\ & \X[0]~combout\)

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "1001011001011010")
-- pragma translate_on
PORT MAP (
	dataa => \Y[1]~combout\,
	datab => \Y[0]~combout\,
	datac => \X[1]~combout\,
	datad => \X[0]~combout\,
	combout => \result~221\);

\Y[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_Y(2),
	combout => \Y[2]~combout\);

\X[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_X(2),
	combout => \X[2]~combout\);

\S2~18_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \S2~18\ = \Y[1]~combout\ & (\X[1]~combout\ # \Y[0]~combout\ & \X[0]~combout\) # !\Y[1]~combout\ & \Y[0]~combout\ & \X[1]~combout\ & \X[0]~combout\

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "1110100010100000")
-- pragma translate_on
PORT MAP (
	dataa => \Y[1]~combout\,
	datab => \Y[0]~combout\,
	datac => \X[1]~combout\,
	datad => \X[0]~combout\,
	combout => \S2~18\);

\result~222_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \result~222\ = \Y[2]~combout\ $ \X[2]~combout\ $ \S2~18\

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "1100001100111100")
-- pragma translate_on
PORT MAP (
	datab => \Y[2]~combout\,
	datac => \X[2]~combout\,
	datad => \S2~18\,
	combout => \result~222\);

\X[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_X(3),
	combout => \X[3]~combout\);

\S3~68_I\ : cycloneii_lcell_comb
-- Equation(s):
-- \S3~68\ = \X[2]~combout\ & \S2~18\

-- pragma translate_off
GENERIC MAP (
	sum_lutc_input => "datac",
	lut_mask => "1111000000000000")
-- pragma translate_on
PORT MAP (
	datac => \X[2]~combout\,
	datad => \S2~18\,
	combout => \S3~68\);

\Y[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",