exp9.map.eqn

四人抢答器

-- Copyright (C) 1991-2005 Altera Corporation
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-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L37 is result~0
A1L37 = X[0] $ Y[0];


--A1L39 is result~221
A1L39 = X[1] $ Y[1] $ (X[0] & Y[0]);


--A1L42 is S2~18
A1L42 = X[1] & (Y[1] # Y[0] & X[0]) # !X[1] & Y[0] & X[0] & Y[1];


--A1L40 is result~222
A1L40 = A1L42 $ X[2] $ Y[2];


--A1L43 is S3~67
A1L43 = Y[2] & (A1L42 # X[2]);


--A1L44 is S3~68
A1L44 = A1L42 & X[2];


--A1L38 is result~3
A1L38 = X[3] $ Y[3] $ (A1L43 # A1L44);


--A1L41 is result~223
A1L41 = X[3] & (A1L44 # A1L43 # Y[3]) # !X[3] & Y[3] & (A1L44 # A1L43);


--A1L48Q is SEG_SEL[0]~reg0
A1L48Q = DFFEAS(A1L47, Clk,  ,  ,  ,  ,  ,  ,  );


--A1L50Q is SEG_SEL[1]~reg0
A1L50Q = DFFEAS(A1L1, Clk,  ,  ,  ,  ,  ,  ,  );


--A1L53Q is SEG_SEL[2]~reg0
A1L53Q = DFFEAS(A1L52, Clk,  ,  ,  ,  ,  ,  ,  );


--C1_q_a[6] is altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 16, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[6]_PORT_A_address = BUS(A1L4, A1L10, A1L12, A1L15);
C1_q_a[6]_PORT_A_address_reg = DFFE(C1_q_a[6]_PORT_A_address, C1_q_a[6]_clock_0, , , );
C1_q_a[6]_clock_0 = Clk;
C1_q_a[6]_PORT_A_data_out = MEMORY(, , C1_q_a[6]_PORT_A_address_reg, , , , , , C1_q_a[6]_clock_0, , , , , );
C1_q_a[6] = C1_q_a[6]_PORT_A_data_out[0];


--C1_q_a[5] is altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 16, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[5]_PORT_A_address = BUS(A1L4, A1L10, A1L12, A1L15);
C1_q_a[5]_PORT_A_address_reg = DFFE(C1_q_a[5]_PORT_A_address, C1_q_a[5]_clock_0, , , );
C1_q_a[5]_clock_0 = Clk;
C1_q_a[5]_PORT_A_data_out = MEMORY(, , C1_q_a[5]_PORT_A_address_reg, , , , , , C1_q_a[5]_clock_0, , , , , );
C1_q_a[5] = C1_q_a[5]_PORT_A_data_out[0];


--C1_q_a[4] is altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 16, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[4]_PORT_A_address = BUS(A1L4, A1L10, A1L12, A1L15);
C1_q_a[4]_PORT_A_address_reg = DFFE(C1_q_a[4]_PORT_A_address, C1_q_a[4]_clock_0, , , );
C1_q_a[4]_clock_0 = Clk;
C1_q_a[4]_PORT_A_data_out = MEMORY(, , C1_q_a[4]_PORT_A_address_reg, , , , , , C1_q_a[4]_clock_0, , , , , );
C1_q_a[4] = C1_q_a[4]_PORT_A_data_out[0];


--C1_q_a[3] is altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 16, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[3]_PORT_A_address = BUS(A1L4, A1L10, A1L12, A1L15);
C1_q_a[3]_PORT_A_address_reg = DFFE(C1_q_a[3]_PORT_A_address, C1_q_a[3]_clock_0, , , );
C1_q_a[3]_clock_0 = Clk;
C1_q_a[3]_PORT_A_data_out = MEMORY(, , C1_q_a[3]_PORT_A_address_reg, , , , , , C1_q_a[3]_clock_0, , , , , );
C1_q_a[3] = C1_q_a[3]_PORT_A_data_out[0];


--C1_q_a[2] is altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 16, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[2]_PORT_A_address = BUS(A1L4, A1L10, A1L12, A1L15);
C1_q_a[2]_PORT_A_address_reg = DFFE(C1_q_a[2]_PORT_A_address, C1_q_a[2]_clock_0, , , );
C1_q_a[2]_clock_0 = Clk;
C1_q_a[2]_PORT_A_data_out = MEMORY(, , C1_q_a[2]_PORT_A_address_reg, , , , , , C1_q_a[2]_clock_0, , , , , );
C1_q_a[2] = C1_q_a[2]_PORT_A_data_out[0];


--C1_q_a[1] is altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 16, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[1]_PORT_A_address = BUS(A1L4, A1L10, A1L12, A1L15);
C1_q_a[1]_PORT_A_address_reg = DFFE(C1_q_a[1]_PORT_A_address, C1_q_a[1]_clock_0, , , );
C1_q_a[1]_clock_0 = Clk;
C1_q_a[1]_PORT_A_data_out = MEMORY(, , C1_q_a[1]_PORT_A_address_reg, , , , , , C1_q_a[1]_clock_0, , , , , );
C1_q_a[1] = C1_q_a[1]_PORT_A_data_out[0];


--C1_q_a[0] is altsyncram:Disp_Decode_rtl_0|altsyncram_77l:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 16, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 7
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[0]_PORT_A_address = BUS(A1L4, A1L10, A1L12, A1L15);
C1_q_a[0]_PORT_A_address_reg = DFFE(C1_q_a[0]_PORT_A_address, C1_q_a[0]_clock_0, , , );
C1_q_a[0]_clock_0 = Clk;
C1_q_a[0]_PORT_A_data_out = MEMORY(, , C1_q_a[0]_PORT_A_address_reg, , , , , , C1_q_a[0]_clock_0, , , , , );
C1_q_a[0] = C1_q_a[0]_PORT_A_data_out[0];


--A1L1 is add~297
A1L1 = A1L48Q $ A1L50Q;


--A1L52 is SEG_SEL[2]~15
A1L52 = A1L53Q $ (A1L48Q & A1L50Q);


--A1L3 is Disp_Temp[0]~1340
A1L3 = A1L38 & (A1L39 & (A1L40 # !A1L41) # !A1L39 & A1L40 & !A1L41) # !A1L38 & (!A1L40 & A1L41);


--A1L4 is Disp_Temp[0]~1341
A1L4 = A1L48Q & (A1L3 & !A1L50Q) # !A1L48Q & (A1L37 # !A1L50Q);


--A1L5 is Disp_Temp[0]~1342
A1L5 = A1L41 & (A1L40 # A1L38);


--A1L6 is Disp_Temp[1]~1343
A1L6 = A1L48Q # A1L39 & (!A1L16 # !A1L41);


--A1L26 is LessThan~581
A1L26 = !A1L39 & !A1L40 # !A1L38;


--A1L7 is Disp_Temp[1]~1344
A1L7 = A1L26 & !A1L41 & !A1L48Q;


--A1L8 is Disp_Temp[1]~1345
A1L8 = A1L39 & (A1L7 # A1L5 & A1L6) # !A1L39 & A1L5 & A1L6;


--A1L9 is Disp_Temp[1]~1346
A1L9 = !A1L48Q & !A1L5 & (A1L41 # !A1L26);


--A1L10 is Disp_Temp[1]~1347
A1L10 = A1L8 # A1L9 & !A1L39 # !A1L1;


--A1L11 is Disp_Temp[2]~1348
A1L11 = A1L41 & !A1L40 & (A1L38 # !A1L39) # !A1L41 & A1L40 & (A1L39 # !A1L38);


--A1L12 is Disp_Temp[2]~1349
A1L12 = A1L50Q & A1L11 & !A1L48Q;


--A1L13 is Disp_Temp[3]~1350
A1L13 = A1L41 & A1L16 & !A1L39 & !A1L48Q;


--A1L14 is Disp_Temp[3]~1351
A1L14 = A1L13 # A1L38 & A1L7 # !A1L1;


--A1L27 is LessThan~582
A1L27 = A1L39 # A1L42 $ X[2] $ Y[2];


--A1L15 is Disp_Temp[3]~1352
A1L15 = A1L14 # A1L9 & (A1L38 $ A1L27);


--A1L16 is Disp_Temp[3]~1353
A1L16 = A1L38 & (A1L42 $ X[2] $ Y[2]);


--A1L47 is SEG_SEL[0]~16
A1L47 = !A1L48Q;


--X[0] is X[0]
--operation mode is input

X[0] = INPUT();


--Y[0] is Y[0]
--operation mode is input

Y[0] = INPUT();


--X[1] is X[1]
--operation mode is input

X[1] = INPUT();


--Y[1] is Y[1]
--operation mode is input

Y[1] = INPUT();


--X[2] is X[2]
--operation mode is input

X[2] = INPUT();


--Y[2] is Y[2]
--operation mode is input

Y[2] = INPUT();


--X[3] is X[3]
--operation mode is input

X[3] = INPUT();


--Y[3] is Y[3]
--operation mode is input

Y[3] = INPUT();


--Clk is Clk
--operation mode is input

Clk = INPUT();


--result[0] is result[0]
--operation mode is output

result[0] = OUTPUT(A1L37);


--result[1] is result[1]
--operation mode is output

result[1] = OUTPUT(A1L39);


--result[2] is result[2]
--operation mode is output

result[2] = OUTPUT(A1L40);


--result[3] is result[3]
--operation mode is output

result[3] = OUTPUT(A1L38);


--result[4] is result[4]
--operation mode is output

result[4] = OUTPUT(A1L41);


--result[5] is result[5]
--operation mode is output

result[5] = OUTPUT(GND);


--result[6] is result[6]
--operation mode is output

result[6] = OUTPUT(GND);


--result[7] is result[7]
--operation mode is output

result[7] = OUTPUT(GND);


--SEG_SEL[0] is SEG_SEL[0]
--operation mode is output

SEG_SEL[0] = OUTPUT(A1L48Q);


--SEG_SEL[1] is SEG_SEL[1]
--operation mode is output

SEG_SEL[1] = OUTPUT(A1L50Q);


--SEG_SEL[2] is SEG_SEL[2]
--operation mode is output

SEG_SEL[2] = OUTPUT(A1L53Q);


--Display[0] is Display[0]
--operation mode is output

Display[0] = OUTPUT(C1_q_a[6]);


--Display[1] is Display[1]
--operation mode is output

Display[1] = OUTPUT(C1_q_a[5]);


--Display[2] is Display[2]
--operation mode is output

Display[2] = OUTPUT(C1_q_a[4]);


--Display[3] is Display[3]
--operation mode is output

Display[3] = OUTPUT(C1_q_a[3]);


--Display[4] is Display[4]
--operation mode is output

Display[4] = OUTPUT(C1_q_a[2]);


--Display[5] is Display[5]
--operation mode is output

Display[5] = OUTPUT(C1_q_a[1]);


--Display[6] is Display[6]
--operation mode is output

Display[6] = OUTPUT(C1_q_a[0]);


--Display[7] is Display[7]
--operation mode is output

Display[7] = OUTPUT(GND);