exp9.qsf

四人抢答器

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		exp9_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C8
set_global_assignment -name TOP_LEVEL_ENTITY exp9
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:56:30  OCTOBER 18, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 5.1
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name VHDL_FILE exp9.vhd
set_location_assignment PIN_AA9 -to X[0]
set_location_assignment PIN_AB8 -to X[1]
set_location_assignment PIN_AD23 -to X[2]
set_location_assignment PIN_AC22 -to X[3]
set_location_assignment PIN_AB10 -to Y[0]
set_location_assignment PIN_AA10 -to Y[1]
set_location_assignment PIN_AA11 -to Y[2]
set_location_assignment PIN_AB12 -to Y[3]
set_location_assignment PIN_N2 -to Clk
set_location_assignment PIN_V17 -to Display[0]
set_location_assignment PIN_W16 -to Display[1]
set_location_assignment PIN_W15 -to Display[2]
set_location_assignment PIN_L10 -to Display[3]
set_location_assignment PIN_V14 -to Display[4]
set_location_assignment PIN_V13 -to Display[5]
set_location_assignment PIN_W12 -to Display[6]
set_location_assignment PIN_U12 -to SEG_SEL[0]
set_location_assignment PIN_V20 -to SEG_SEL[1]
set_location_assignment PIN_V21 -to SEG_SEL[2]
set_location_assignment PIN_AA12 -to result[0]
set_location_assignment PIN_AA13 -to result[1]
set_location_assignment PIN_AA14 -to result[2]
set_location_assignment PIN_AB15 -to result[3]
set_location_assignment PIN_U18 -to result[4]
set_location_assignment PIN_AA15 -to result[5]
set_location_assignment PIN_AA16 -to result[6]
set_location_assignment PIN_AA17 -to result[7]