📄 mem_interface_top_data_path_iobs_0.txt
字号:
.WRITE_DATA_RISE (wr_data_rise[5]),
.WRITE_DATA_FALL (wr_data_fall[5]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[5]),
.READ_DATA_RISE (rd_data_rise[5]),
.READ_DATA_FALL (rd_data_fall[5])
);
mem_interface_top_v4_dq_iob v4_dq_iob6
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[6]),
.WRITE_DATA_FALL (wr_data_fall[6]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[6]),
.READ_DATA_RISE (rd_data_rise[6]),
.READ_DATA_FALL (rd_data_fall[6])
);
mem_interface_top_v4_dq_iob v4_dq_iob7
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[7]),
.WRITE_DATA_FALL (wr_data_fall[7]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[7]),
.READ_DATA_RISE (rd_data_rise[7]),
.READ_DATA_FALL (rd_data_fall[7])
);
mem_interface_top_v4_dq_iob v4_dq_iob8
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[8]),
.WRITE_DATA_FALL (wr_data_fall[8]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[8]),
.READ_DATA_RISE (rd_data_rise[8]),
.READ_DATA_FALL (rd_data_fall[8])
);
mem_interface_top_v4_dq_iob v4_dq_iob9
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[9]),
.WRITE_DATA_FALL (wr_data_fall[9]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[9]),
.READ_DATA_RISE (rd_data_rise[9]),
.READ_DATA_FALL (rd_data_fall[9])
);
mem_interface_top_v4_dq_iob v4_dq_iob10
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[10]),
.WRITE_DATA_FALL (wr_data_fall[10]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[10]),
.READ_DATA_RISE (rd_data_rise[10]),
.READ_DATA_FALL (rd_data_fall[10])
);
mem_interface_top_v4_dq_iob v4_dq_iob11
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[11]),
.WRITE_DATA_FALL (wr_data_fall[11]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[11]),
.READ_DATA_RISE (rd_data_rise[11]),
.READ_DATA_FALL (rd_data_fall[11])
);
mem_interface_top_v4_dq_iob v4_dq_iob12
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[12]),
.WRITE_DATA_FALL (wr_data_fall[12]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[12]),
.READ_DATA_RISE (rd_data_rise[12]),
.READ_DATA_FALL (rd_data_fall[12])
);
mem_interface_top_v4_dq_iob v4_dq_iob13
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[13]),
.WRITE_DATA_FALL (wr_data_fall[13]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[13]),
.READ_DATA_RISE (rd_data_rise[13]),
.READ_DATA_FALL (rd_data_fall[13])
);
mem_interface_top_v4_dq_iob v4_dq_iob14
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[14]),
.WRITE_DATA_FALL (wr_data_fall[14]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[14]),
.READ_DATA_RISE (rd_data_rise[14]),
.READ_DATA_FALL (rd_data_fall[14])
);
mem_interface_top_v4_dq_iob v4_dq_iob15
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[15]),
.WRITE_DATA_FALL (wr_data_fall[15]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[15]),
.READ_DATA_RISE (rd_data_rise[15]),
.READ_DATA_FALL (rd_data_fall[15])
);
mem_interface_top_v4_dq_iob v4_dq_iob16
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[16]),
.WRITE_DATA_FALL (wr_data_fall[16]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[16]),
.READ_DATA_RISE (rd_data_rise[16]),
.READ_DATA_FALL (rd_data_fall[16])
);
mem_interface_top_v4_dq_iob v4_dq_iob17
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[17]),
.WRITE_DATA_FALL (wr_data_fall[17]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[17]),
.READ_DATA_RISE (rd_data_rise[17]),
.READ_DATA_FALL (rd_data_fall[17])
);
mem_interface_top_v4_dq_iob v4_dq_iob18
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[18]),
.WRITE_DATA_FALL (wr_data_fall[18]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[18]),
.READ_DATA_RISE (rd_data_rise[18]),
.READ_DATA_FALL (rd_data_fall[18])
);
mem_interface_top_v4_dq_iob v4_dq_iob19
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[19]),
.WRITE_DATA_FALL (wr_data_fall[19]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[19]),
.READ_DATA_RISE (rd_data_rise[19]),
.READ_DATA_FALL (rd_data_fall[19])
);
mem_interface_top_v4_dq_iob v4_dq_iob20
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[20]),
.WRITE_DATA_FALL (wr_data_fall[20]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[20]),
.READ_DATA_RISE (rd_data_rise[20]),
.READ_DATA_FALL (rd_data_fall[20])
);
mem_interface_top_v4_dq_iob v4_dq_iob21
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[21]),
.WRITE_DATA_FALL (wr_data_fall[21]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[21]),
.READ_DATA_RISE (rd_data_rise[21]),
.READ_DATA_FALL (rd_data_fall[21])
);
mem_interface_top_v4_dq_iob v4_dq_iob22
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[22]),
.WRITE_DATA_FALL (wr_data_fall[22]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[22]),
.READ_DATA_RISE (rd_data_rise[22]),
.READ_DATA_FALL (rd_data_fall[22])
);
mem_interface_top_v4_dq_iob v4_dq_iob23
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[23]),
.WRITE_DATA_FALL (wr_data_fall[23]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[23]),
.READ_DATA_RISE (rd_data_rise[23]),
.READ_DATA_FALL (rd_data_fall[23])
);
mem_interface_top_v4_dq_iob v4_dq_iob24
(
.CLK (CLK),
.CLK90 (CLK90),
.RESET (RESET90),
.DATA_DLYINC (data_idelay_inc[0]),
.DATA_DLYCE (data_idelay_ce[0]),
.DATA_DLYRST (data_idelay_rst[0]),
.WRITE_DATA_RISE (wr_data_rise[24]),
.WRITE_DATA_FALL (wr_data_fall[24]),
.CTRL_WREN (wr_en),
.DDR_DQ (DDR_DQ[24]),
.READ_DATA_RISE (rd_data_rise[24]),
.READ_DATA_FALL (rd_data_fall[24])
);
mem_interface_top_v4_dq_iob v4_dq_iob25
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