mem_interface_top_test_bench_0.txt

基于Xilinx FPGA的DDRSDRAM的Verilog控制代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_test_bench_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Test bench to compare the write and the read data and generate
//              an error flag.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_test_bench_0
  (
   input                                CLK,
   input                                RESET,
   input                                WDF_ALMOST_FULL,
   input                                AF_ALMOST_FULL,
   input [2:0]                          BURST_LENGTH,
   input                                READ_DATA_VALID,
   input [(`data_width*2)-1:0]          READ_DATA_FIFO_OUT,
   output [35:0]                        APP_AF_ADDR,
   output                               APP_AF_WREN,
   output [(`data_width*2)-1:0]         APP_WDF_DATA,
   output [(`data_mask_width*2)-1:0]    APP_MASK_DATA,
   output                               APP_WDF_WREN,
   output                               ERROR
   );



   reg [2:0]                            state;
   reg [3:0]                            burst_count;
   reg                                  write_data_en;
   reg                                  write_addr_en;
   reg [3:0]                            state_cnt;
   reg                                  rst_r;


   wire [(`data_width*2)-1:0]           app_cmp_data;
   wire [3:0]                           burst_len;


   localparam                           idle =  3'b000;
   localparam                           write=  3'b001;
   localparam                           read =  3'b010;

   assign burst_len = BURST_LENGTH;

   always @( posedge CLK)
     rst_r <= RESET;


   // State Machine for writing to WRITE DATA & ADDRESS FIFOs
   always @ (posedge CLK) begin
      if (rst_r == 1'b1) begin  // State Machine in IDLE state
         write_data_en <= 1'b0;
         write_addr_en <= 1'b0;
         state[2:0]     <= idle;
         state_cnt <= 4'b0000;
      end
      else begin
         case (state[2:0])
           3'b000: begin // idle
              write_data_en <= 1'b0;
              write_addr_en <= 1'b0;
              if (WDF_ALMOST_FULL == 1'b0 && AF_ALMOST_FULL == 1'b0) begin
                 state[2:0]       <= write;
                 burst_count[3:0] <=  burst_len; // Burst length divided by 2
              end
              else begin
                 state[2:0]       <= idle;
                 burst_count[3:0] <= 4'b0000;
              end
           end

           3'b001: begin // write
              if (WDF_ALMOST_FULL == 1'b0 && AF_ALMOST_FULL == 1'b0) begin
                 if(state_cnt == 4'd8) begin
                    state <= read;
                    state_cnt <= 4'd0;
                    if(burst_len == 3'd1)
                      write_data_en    <= 1'b0;
                    else
                      write_data_en    <= 1'b1;
                 end
                 else begin
                    state[2:0]       <= write;
                    write_data_en    <= 1'b1;
                 end
                 if ((burst_count[3:0] != 4'b0000) && (burst_len != 3'd1))
                   burst_count[3:0] <= burst_count[3:0] - 1'b1;
                 else begin
                    if(burst_len == 3'd1)
                      burst_count[3:0] <=  burst_len;
                    else
                      burst_count[3:0] <=  burst_len - 1'b1;
                 end

                 if ((burst_count[3:0] == 4'b0001) && (state_cnt < 4'd8)) begin
                    write_addr_en  <= 1'b1;
                    state_cnt <= state_cnt + 1'b1;
                 end
                 else
                   write_addr_en  <= 1'b0;
              end
              else begin
                 write_addr_en    <= 1'b0;
                 write_data_en    <= 1'b0;
              end
           end

           3'b010: begin // read
              if ( AF_ALMOST_FULL == 1'b0) begin
                 if(state_cnt == 4'd8) begin
                    write_addr_en  <= 1'b0;
                    if (WDF_ALMOST_FULL == 1'b0) begin
                       state_cnt <= 4'd0;
                       state <= write;
                    end
                    else begin
                       state_cnt <= 4'd0;
                       state <= idle;
                    end
                 end
                 else begin
                    state[2:0]       <= read;
                    write_addr_en  <= 1'b1;
                    write_data_en    <= 1'b0;
                    state_cnt <= state_cnt + 1;
                 end
              end
              else begin
                 write_addr_en  <= 1'b0;
                 write_data_en    <= 1'b0;
              end
           end

           default: begin
              write_data_en <= 1'b0;
              write_addr_en <= 1'b0;
              state[2:0]    <= idle;
           end
         endcase
      end
   end

   mem_interface_top_cmp_rd_data_0 cmp_rd_data_00
     (
      .CLK                      (CLK),
      .RESET                    (RESET),
      .READ_DATA_VALID          (READ_DATA_VALID),
      .APP_COMPARE_DATA         (app_cmp_data),
      .READ_DATA_FIFO_OUT       (READ_DATA_FIFO_OUT),
      .ERROR                    (ERROR)
      );

   mem_interface_top_backend_rom_0 backend_rom_00
     (
      .clk0                     (CLK),
      .rst                      (RESET),
      .bkend_data_en            (write_data_en),
      .bkend_wraddr_en          (write_addr_en),
      .bkend_rd_data_valid      (READ_DATA_VALID),
      .app_af_addr              (APP_AF_ADDR),
      .app_af_WrEn              (APP_AF_WREN),
      .app_Wdf_data             (APP_WDF_DATA),
      .app_mask_data            (APP_MASK_DATA),
      .app_compare_data         (app_cmp_data),
      .app_Wdf_WrEn             (APP_WDF_WREN)
      );


endmodule