mem_interface_top_v4_dq_iob.txt

基于Xilinx FPGA的DDRSDRAM的Verilog控制代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_v4_dq_iob.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Places the data in the IOBs.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps
module mem_interface_top_v4_dq_iob
  (
   input        CLK,
   input        CLK90,
   input        RESET,
   input        DATA_DLYINC,
   input        DATA_DLYCE,
   input        DATA_DLYRST,
   input        WRITE_DATA_RISE,
   input        WRITE_DATA_FALL,
   input        CTRL_WREN,
   inout        DDR_DQ,
   output       READ_DATA_RISE,
   output       READ_DATA_FALL
   );


   wire         dq_in;
   wire         dq_out;
   wire         dq_delayed;
   wire         write_en_L;
   wire         write_en_L_r1;
   wire         vcc;
   wire         gnd;

   assign       vcc        = 1'b1;
   assign       gnd        = 1'b0;
   assign       write_en_L = ~CTRL_WREN;

   defparam     oddr_dq.SRTYPE = "SYNC";
   defparam     oddr_dq.DDR_CLK_EDGE = "SAME_EDGE";


   ODDR oddr_dq
     (
      .Q  (dq_out),
      .C  (CLK90),
      .CE (vcc),
      .D1 (WRITE_DATA_RISE),
      .D2 (WRITE_DATA_FALL),
      .R  (gnd),
      .S  (gnd)
      );

   FDCE tri_state_dq
     (

      .D   (write_en_L),
      .CLR (gnd),
      .C   (CLK90),
      .Q   (write_en_L_r1),
      .CE  (vcc)
      );


   IOBUF  iobuf_dq
     (
      .I  (dq_out),
      .T  (write_en_L_r1),
      .IO (DDR_DQ),
      .O  (dq_in)
      );


   defparam     idelay_dq.IOBDELAY_TYPE = "VARIABLE";
   defparam     idelay_dq.IOBDELAY_VALUE = 0;

   IDELAY idelay_dq
     (
      .O   (dq_delayed),
      .I   (dq_in),
      .C   (CLK),
      .CE  (DATA_DLYCE),
      .INC (DATA_DLYINC),
      .RST (DATA_DLYRST)
      );


   defparam     iddr_dq.SRTYPE = "SYNC";
   defparam     iddr_dq.DDR_CLK_EDGE = "SAME_EDGE_PIPELINED";

   IDDR iddr_dq
     (
      .Q1 (READ_DATA_RISE),
      .Q2 (READ_DATA_FALL),
      .C  (CLK),
      .CE (vcc),
      .D  (dq_delayed),
      .R  (gnd),
      .S  (gnd)
      );

endmodule