mem_interface_top_addr_gen_0.txt

基于Xilinx FPGA的DDRSDRAM的Verilog控制代码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_addr_gen.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:15 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: The address for the memory and the various user commands can be
//              given through this module. It instantiates the block RAM which
//              stores all the information in particular sequence. The data
//              stored should be in a sequence starting from
//              LSB: column address, row address, bank address, chip address,
//              commands, and the row conflict information.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps


 module mem_interface_top_addr_gen
   (
    input               clk0,
    input               rst,
    input               bkend_wraddr_en,
    output reg [35:0]   app_af_addr,
    output reg          app_af_WrEn
    );


   reg [5:0] wr_addr_count;
   reg       bkend_wraddr_en_reg;
   reg       wr_rd_addr_en_reg;
   reg       bkend_wraddr_en_3r;
   reg       rst_r;

   wire [8:0] wr_rd_addr;
   wire       wr_rd_addr_en;
   wire [31:0] unused_data_in;
   wire [3:0]  unused_data_in_p;
   wire        gnd;
   wire [35:0] addr_out;

   assign  unused_data_in = 32'h00000000;
   assign  unused_data_in_p = 4'h0;
   assign  gnd = 1'b0;

   //ADDRESS generation for Write and Read Address FIFOs

   // RAMB16_S36 is set to 512x36 mode

   // INITP_00 [2:0]
   // read -5
   // write -4
   // lmr - 0
   // pre -2
   // ref -1
   // active -3

   always @( posedge clk0 )
     rst_r <= rst;

   defparam
         wr_rd_addr_lookup.INIT_00 = 256'h0003C154_0003C198_0003C088_0003C0EC_00023154_00023198_00023088_000230EC,
         wr_rd_addr_lookup.INIT_01 = 256'h00023154_00023198_00023088_000230EC_0003C154_0003C198_0003C088_0003C0EC,
         wr_rd_addr_lookup.INIT_02 = 256'h0083C154_0083C198_0083C088_0083C0EC_00823154_00823198_00823088_008230EC,
         wr_rd_addr_lookup.INIT_03 = 256'h0083C154_0083C198_0083C088_0083C0EC_00823154_00823198_00823088_008230EC,
         wr_rd_addr_lookup.INIT_04 = 256'h0043C154_0043C198_0043C088_0043C0EC_00423154_00423198_00423088_004230EC,
         wr_rd_addr_lookup.INIT_05 = 256'h0043C154_0043C198_0043C088_0043C0EC_00423154_00423198_00423088_004230EC,
         wr_rd_addr_lookup.INIT_06 = 256'h00C3C154_00C3C198_00C3C088_00C3C0EC_00C23154_00C23198_00C23088_00C230EC,
         wr_rd_addr_lookup.INIT_07 = 256'h00C3C154_00C3C198_00C3C088_00C3C0EC_00C23154_00C23198_00C23088_00C230EC,

         wr_rd_addr_lookup.INITP_00 = 256'h55555555_44444444_55555555_44444444_55555555_44444444_55555555_44444444;


   RAMB16_S36 wr_rd_addr_lookup
     (
      .DO    (addr_out[31:0]),
      .DOP   (addr_out[35:32]),
      .ADDR  (wr_rd_addr[8:0]),
      .CLK   (clk0),
      .DI    (unused_data_in[31:0]),
      .DIP   (unused_data_in_p[3:0]),
      .EN    (wr_rd_addr_en_reg),
      .SSR   (gnd),
      .WE    (gnd)
      );


   assign wr_rd_addr_en = (bkend_wraddr_en == 1'b1);

   always @ (posedge clk0) begin
      if (rst_r) begin
         wr_rd_addr_en_reg <= 1'b0;
      end else begin
         wr_rd_addr_en_reg <= wr_rd_addr_en;
      end
   end

   //register backend enables
   always @ (posedge clk0) begin
      if (rst_r) begin
         bkend_wraddr_en_reg <= 1'b0;
         bkend_wraddr_en_3r  <= 1'b0;
      end
      else begin
         bkend_wraddr_en_reg <= bkend_wraddr_en;
         bkend_wraddr_en_3r  <= bkend_wraddr_en_reg;
      end
   end

   // Fifo enables
   always @ (posedge clk0) begin
      if (rst_r) begin
         app_af_WrEn <= 1'b0;
      end
      else begin
         app_af_WrEn <= bkend_wraddr_en_3r;

      end
   end

   // FIFO addresses
   always @ (posedge clk0) begin
      if (rst_r) begin
         app_af_addr <= 36'h00000;
      end
      else if (bkend_wraddr_en_3r) begin
         app_af_addr <= addr_out;
      end
      else begin
              app_af_addr <= 36'h00000;
      end
   end

   // address input
   always @ (posedge clk0) begin
      if (rst_r) begin
         wr_addr_count[5:0] <= 6'b111111;
      end else if (bkend_wraddr_en) begin
         wr_addr_count[5:0] <= wr_addr_count[5:0] + 1;
      end else begin
         wr_addr_count[5:0] <= wr_addr_count[5:0];
      end
   end


   assign wr_rd_addr[8:0] = (bkend_wraddr_en_reg) ? {3'b000,wr_addr_count[5:0]} :
                            9'b000000000;

endmodule