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来自「基于FPGA的SDRAM控制器Verilog代码」· 代码 · 共 12 行

# Reading D:/Program Files/ModelSim/win32/../tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "E:/pWs餩~剣