system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

Net fpga_0_DDR2_SDRAM_DDR2_DQ<59> LOC=L26;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<59> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<60> LOC=J27;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<60> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<61> LOC=M25;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<61> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<62> LOC=L25;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<62> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<63> LOC=L24;
Net fpga_0_DDR2_SDRAM_DDR2_DQ<63> IOSTANDARD = SSTL18_II;

#### Module SysACE_CompactFlash constraints

Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH17;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=G5;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=N7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=N5;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=P5;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=R6;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=M6;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=L6;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=P9;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=T8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=J7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=H7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=R7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=U7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=P7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=P6;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=R8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=L5;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=L4;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=K6;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=J5;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=T6;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=K7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=J6;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=M5;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=N8;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=R9;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=M7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin TIG;

###############################################################################
# Define multicycle paths - these paths may take longer because additional
# time allowed for logic to settle in calibration/initialization FSM
###############################################################################


# MUX Select for either rising/falling CLK0 for 2nd stage read capture
INST "*/u_phy_calib_0/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
  12ns; #This value must be equal or less than 4 MPMC clock periods...
#...assuming 4 3ns (333MHz) clock periods = 12ns. User modifiable.
# MUX select for read data - optional delay on data to account for byte skews
#INST "*/u_usr_rd_0/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
#TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS   12ns; #This value must be equal or less than 4 MPMC clock periods...
#...assuming 4 3ns (333MHz) clock periods = 12ns. User modifiable.
# Calibration/Initialization complete status flag (for PHY logic only)
INST "*/u_phy_init_0/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO
  FFS 12ns; #This value must be equal or less than 4 MPMC clock periods...
#...assuming 4 3ns (333MHz) clock periods = 12ns. User modifiable.
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO
  FFS 12ns; #This value must be equal or less than 4 MPMC clock periods...
#...assuming 4 3ns (333MHz) clock periods = 12ns. User modifiable.
# Select (address) bits for SRL32 shift registers used in stage3/stage4
# calibration
INST "*/u_phy_calib_0/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS 12ns; #This value must be equal or less than 4 MPMC clock periods...
#...assuming 4 3ns (333MHz) clock periods = 12ns. User modifiable.
INST "*/u_phy_calib_0/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS 12ns; #This value must be equal or less than 4 MPMC clock periods...
#...assuming 4 3ns (333MHz) clock periods = 12ns. User modifiable.
INST "*/u_phy_calib_0/gen_cal_rden_dly*.u_ff_cal_rden_dly"
TNM = "TNM_CAL_RDEN_DLY";
TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
  12ns; #This value must be equal or less than 4 MPMC clock periods...
#...assuming 4 3ns (333MHz) clock periods = 12ns. User modifiable.

###############################################################################
# DQS Read Postamble Glitch Squelch circuit related constraints
###############################################################################

###############################################################################
# LOC placement of DQS-squelch related IDDR and IDELAY elements
# Each circuit can be located at any of the following locations:
#  1. Ununsed "N"-side of DQS diff pair I/O
#  2. DM data mask (output only, input side is free for use)
#  3. Any output-only site
###############################################################################

INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y96";
INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y96";
INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y58";
INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y58";
INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y62";
INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y62";
INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y100";
INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y100";
INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y102";
INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y102";
INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y256";
INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y256";
INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y260";
INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y260";
INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce"	LOC = "ILOGIC_X0Y262";
INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce"	LOC = "IODELAY_X0Y262";

###############################################################################
# LOC and timing constraints for flop driving DQS CE enable signal
# from fabric logic. Even though the absolute delay on this path is
# calibrated out (when synchronizing this output to DQS), the delay
# should still be kept as low as possible to reduce post-calibration
# voltage/temp variations - these are roughly proportional to the
# absolute delay of the path
###############################################################################

INST "*/u_phy_calib_0/gen_gate[0].u_en_dqs_ff"	LOC = SLICE_X0Y48;
INST "*/u_phy_calib_0/gen_gate[1].u_en_dqs_ff"	LOC = SLICE_X0Y29;
INST "*/u_phy_calib_0/gen_gate[2].u_en_dqs_ff"	LOC = SLICE_X0Y31;
INST "*/u_phy_calib_0/gen_gate[3].u_en_dqs_ff"	LOC = SLICE_X0Y50;
INST "*/u_phy_calib_0/gen_gate[4].u_en_dqs_ff"	LOC = SLICE_X0Y51;
INST "*/u_phy_calib_0/gen_gate[5].u_en_dqs_ff"	LOC = SLICE_X0Y128;
INST "*/u_phy_calib_0/gen_gate[6].u_en_dqs_ff"	LOC = SLICE_X0Y130;
INST "*/u_phy_calib_0/gen_gate[7].u_en_dqs_ff"	LOC = SLICE_X0Y131;

# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
# two parts to this path: (1) from fabric flop to IDELAY, (2) from
# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
# A single number is used for all speed grades - value based on 333MHz.
# This can be relaxed for lower frequencies.
NET "*/u_phy_io_0/en_dqs*" MAXDELAY = 600 ps;
NET "*/u_phy_io_0/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;

###############################################################################
# "Half-cycle" path constraint from IDDR to CE pin for all DQ IDDR's
# for DQS Read Postamble Glitch Squelch circuit
###############################################################################

# Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack
#  where slack account for rise-time of DQS on board. For now assume slack =
#  0.400ns (based on initial SPICE simulations, assumes use of ODT), so
#  time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.90 ns;

###############################################################################
# Location constraints for DQ read-data capture flops in fabric (for 2nd
# stage capture)
###############################################################################

INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y42;
INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y43;
INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y45;
INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y46;
INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y41;
INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y42;
INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y44;
INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y44;
INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y28;
INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y32;
INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y33;
INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y34;
INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y26;
INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y28;
INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y33;
INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y34;
INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y35;
INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y36;
INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y38;
INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y39;
INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y36;
INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y37;
INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y38;
INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y39;
INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y46;
INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y49;
INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y53;
INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y55;
INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y49;
INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y52;
INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y54;
INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y56;
INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y52;
INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y56;
INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y58;
INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y59;
INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y54;
INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y57;
INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y58;
INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y59;
INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y120;
INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y121;
INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y122;
INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y123;
INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y120;
INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y121;
INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y123;
INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y124;
INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y124;
INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y126;
INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y132;
INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y133;
INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y125;
INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y126;
INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y133;
INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y134;
INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y134;
INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y136;
INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y137;
INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y138;
INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y135;
INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y136;
INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y138;
INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"	RLOC_ORIGIN = X0Y139;