system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

Net fpga_0_SRAM_Mem_A_pin<30> LOC=K12;
Net fpga_0_SRAM_Mem_A_pin<30> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<30> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<30> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<29> LOC=K13;
Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<28> LOC=H23;
Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<27> LOC=G23;
Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<26> LOC=H12;
Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<25> LOC=J12;
Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<24> LOC=K22;
Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<23> LOC=K23;
Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<22> LOC=K14;
Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<21> LOC=L14;
Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<20> LOC=H22;
Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<19> LOC=G22;
Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<18> LOC=J15;
Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<17> LOC=K16;
Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<16> LOC=K21;
Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<15> LOC=J22;
Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<14> LOC=L16;
Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<13> LOC=L15;
Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<12> LOC=L20;
Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<11> LOC=L21;
Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<10> LOC=AE23;
Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<9> LOC=AE22;
Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<8> LOC=AE12;
Net fpga_0_SRAM_Mem_A_pin<8> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<8> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<8> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_A_pin<7> LOC=AE13;
Net fpga_0_SRAM_Mem_A_pin<7> SLEW = FAST;
Net fpga_0_SRAM_Mem_A_pin<7> DRIVE = 8;
Net fpga_0_SRAM_Mem_A_pin<7> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=J11;
Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=K11;
Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=D10;
Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=D11;
Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_WEN_pin LOC=AF20;
Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST;
Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 12;
Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_OEN_pin LOC=B12;
Net fpga_0_SRAM_Mem_OEN_pin IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=AG22;
Net fpga_0_SRAM_Mem_DQ_pin<0> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=AH22;
Net fpga_0_SRAM_Mem_DQ_pin<1> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=AH12;
Net fpga_0_SRAM_Mem_DQ_pin<2> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=AG13;
Net fpga_0_SRAM_Mem_DQ_pin<3> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=AH20;
Net fpga_0_SRAM_Mem_DQ_pin<4> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=AH19;
Net fpga_0_SRAM_Mem_DQ_pin<5> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=AH14;
Net fpga_0_SRAM_Mem_DQ_pin<6> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=AH13;
Net fpga_0_SRAM_Mem_DQ_pin<7> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=AF15;
Net fpga_0_SRAM_Mem_DQ_pin<8> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=AE16;
Net fpga_0_SRAM_Mem_DQ_pin<9> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=AE21;
Net fpga_0_SRAM_Mem_DQ_pin<10> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=AD20;
Net fpga_0_SRAM_Mem_DQ_pin<11> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=AF16;
Net fpga_0_SRAM_Mem_DQ_pin<12> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=AE17;
Net fpga_0_SRAM_Mem_DQ_pin<13> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=AE19;
Net fpga_0_SRAM_Mem_DQ_pin<14> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=AD19;
Net fpga_0_SRAM_Mem_DQ_pin<15> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST;
Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12;
Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=J9;
Net fpga_0_SRAM_Mem_DQ_pin<16> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=K8;
Net fpga_0_SRAM_Mem_DQ_pin<17> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=K9;
Net fpga_0_SRAM_Mem_DQ_pin<18> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=B13;
Net fpga_0_SRAM_Mem_DQ_pin<19> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=C13;
Net fpga_0_SRAM_Mem_DQ_pin<20> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=G11;
Net fpga_0_SRAM_Mem_DQ_pin<21> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=G12;
Net fpga_0_SRAM_Mem_DQ_pin<22> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=M8;
Net fpga_0_SRAM_Mem_DQ_pin<23> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=L8;
Net fpga_0_SRAM_Mem_DQ_pin<24> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=F11;
Net fpga_0_SRAM_Mem_DQ_pin<25> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=E11;
Net fpga_0_SRAM_Mem_DQ_pin<26> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=M10;
Net fpga_0_SRAM_Mem_DQ_pin<27> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=L9;
Net fpga_0_SRAM_Mem_DQ_pin<28> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=E12;
Net fpga_0_SRAM_Mem_DQ_pin<29> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=E13;
Net fpga_0_SRAM_Mem_DQ_pin<30> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=N10;
Net fpga_0_SRAM_Mem_DQ_pin<31> PULLDOWN;
Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_CEN_pin LOC=J10;
Net fpga_0_SRAM_Mem_CEN_pin IOSTANDARD=LVDCI_33;
Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=H8;
Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD=LVDCI_33;

#### Module Ethernet_MAC constraints

Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J14;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin TIG;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=E34;