system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin TNM_NET = sys_clk_pin;
Net sys_clk_pin LOC = AH15;
Net sys_clk_pin IOSTANDARD=LVCMOS33;
Net sys_rst_pin LOC = E9;
Net sys_rst_pin IOSTANDARD=LVCMOS33;
Net sys_rst_pin PULLUP;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;
Net fpga_0_SRAM_CLK LOC=G8;
Net fpga_0_SRAM_CLK SLEW = FAST;
Net fpga_0_SRAM_CLK DRIVE = 12;
Net fpga_0_SRAM_CLK IOSTANDARD=LVCMOS33;
Net fpga_0_SRAM_CLK_FB LOC=AG21;
Net fpga_0_SRAM_CLK_FB IOSTANDARD=LVCMOS33;

## IO Devices constraints
#### PS/2 mouse and keyboard
Net plb_ps2_controller_0_mouse_clk LOC = R27;
Net plb_ps2_controller_0_mouse_clk IOSTANDARD = LVCMOS18;
Net plb_ps2_controller_0_mouse_data LOC = U26;
Net plb_ps2_controller_0_mouse_data IOSTANDARD = LVCMOS18;
Net plb_ps2_controller_0_key_clk_pin LOC = T26;
Net plb_ps2_controller_0_key_clk_pin IOSTANDARD = LVCMOS18;
Net plb_ps2_controller_0_key_data_pin LOC = T25;
Net plb_ps2_controller_0_key_data_pin IOSTANDARD = LVCMOS18;

#### DVI Constraints
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<0> LOC=AB8;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<0> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<1> LOC=AC8;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<1> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<2> LOC=AN12;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<2> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<3> LOC=AP12;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<3> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<4> LOC=AA9;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<4> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<5> LOC=AA8;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<5> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<6> LOC=AM13;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<6> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<7> LOC=AN13;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<7> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<8> LOC=AA10;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<8> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<9> LOC=AB10;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<9> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<10> LOC=AP14;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<10> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<11> LOC=AN14;
Net plb_npi_vga_controller_0_TFT_LCD_DATA_pin<11> IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_CLK_P_pin LOC=AL11;
Net plb_npi_vga_controller_0_TFT_LCD_CLK_P_pin IOSTANDARD=LVCMOS33;
Net plb_npi_vga_controller_0_TFT_LCD_CLK_P_pin DRIVE = 24;
Net plb_npi_vga_controller_0_TFT_LCD_CLK_P_pin SLEW = FAST;
Net plb_npi_vga_controller_0_TFT_LCD_CLK_N_pin LOC=AL10;
Net plb_npi_vga_controller_0_TFT_LCD_CLK_N_pin IOSTANDARD=LVCMOS33;
Net plb_npi_vga_controller_0_TFT_LCD_CLK_N_pin DRIVE = 24;
Net plb_npi_vga_controller_0_TFT_LCD_CLK_N_pin SLEW = FAST;
Net plb_npi_vga_controller_0_TFT_LCD_HSYNC_pin LOC=AM12;
Net plb_npi_vga_controller_0_TFT_LCD_HSYNC_pin IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_VSYNC_pin LOC=AM11;
Net plb_npi_vga_controller_0_TFT_LCD_VSYNC_pin IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_DE_pin LOC=AE8;
Net plb_npi_vga_controller_0_TFT_LCD_DE_pin IOSTANDARD=LVDCI_33;
Net plb_npi_vga_controller_0_TFT_LCD_reset_pin LOC = AK6;
Net plb_npi_vga_controller_0_TFT_LCD_reset_pin IOSTANDARD = LVCMOS33;
Net plb_npi_vga_controller_0_TFT_LCD_Scl_pin LOC=U27;
Net plb_npi_vga_controller_0_TFT_LCD_Scl_pin SLEW = FAST;
Net plb_npi_vga_controller_0_TFT_LCD_Scl_pin DRIVE = 24;
Net plb_npi_vga_controller_0_TFT_LCD_Scl_pin TIG;
Net plb_npi_vga_controller_0_TFT_LCD_Scl_pin IOSTANDARD=LVCMOS18;
Net plb_npi_vga_controller_0_TFT_LCD_Scl_pin PULLUP;
Net plb_npi_vga_controller_0_TFT_LCD_Sda_pin LOC=T29;
Net plb_npi_vga_controller_0_TFT_LCD_Sda_pin SLEW = FAST;
Net plb_npi_vga_controller_0_TFT_LCD_Sda_pin DRIVE = 24;
Net plb_npi_vga_controller_0_TFT_LCD_Sda_pin TIG;
Net plb_npi_vga_controller_0_TFT_LCD_Sda_pin IOSTANDARD=LVCMOS18;
Net plb_npi_vga_controller_0_TFT_LCD_Sda_pin PULLUP;


#### Module RS232_Uart_1 constraints

Net fpga_0_RS232_Uart_1_RX_pin LOC = AG15;
Net fpga_0_RS232_Uart_1_RX_pin IOSTANDARD=LVCMOS33;
Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20;
Net fpga_0_RS232_Uart_1_TX_pin IOSTANDARD=LVCMOS33;

#### Module LEDs_8Bit constraints

Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC = AE24;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD=LVCMOS18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC = AD24;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD=LVCMOS18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC = AD25;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD=LVCMOS18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC = G16;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD=LVCMOS25;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC = AD26;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD=LVCMOS18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC = G15;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD=LVCMOS25;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC = L18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD=LVCMOS25;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> DRIVE=2;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC = H18;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD=LVCMOS25;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> PULLDOWN;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> SLEW=SLOW;
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> DRIVE=2;

#### Module LEDs_Positions constraints

Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=E8;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLDOWN;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW=SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=AF23;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLDOWN;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW=SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=AG12;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLDOWN;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW=SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=AG23;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLDOWN;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW=SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE=2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=AF13;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLDOWN;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW=SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE=2;

#### Module Push_Buttons_5Bit constraints

Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> LOC = AJ6;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> IOSTANDARD=LVCMOS33;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> PULLDOWN;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> SLEW=SLOW;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> LOC = AJ7;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> IOSTANDARD=LVCMOS33;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> PULLDOWN;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> SLEW=SLOW;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> LOC = V8;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> IOSTANDARD=LVCMOS33;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> PULLDOWN;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> SLEW=SLOW;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> LOC = AK7;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> IOSTANDARD=LVCMOS33;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> PULLDOWN;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> SLEW=SLOW;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> DRIVE=2;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> LOC = U8;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> IOSTANDARD=LVCMOS33;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> PULLDOWN;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> SLEW=SLOW;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> DRIVE=2;

#### Module DIP_Switches_8Bit constraints

Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<0> LOC=U25;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<0> IOSTANDARD=LVCMOS18;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<0> PULLDOWN;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<0> SLEW=SLOW;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<0> DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<1> LOC=AG27;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<1> IOSTANDARD=LVCMOS18;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<1> PULLDOWN;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<1> SLEW=SLOW;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<1> DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<2> LOC=AF25;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<2> IOSTANDARD=LVCMOS18;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<2> PULLDOWN;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<2> SLEW=SLOW;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<2> DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<3> LOC=AF26;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<3> IOSTANDARD=LVCMOS18;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<3> PULLDOWN;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<3> SLEW=SLOW;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<3> DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<4> LOC=AE27;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<4> IOSTANDARD=LVCMOS18;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<4> PULLDOWN;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<4> SLEW=SLOW;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<4> DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<5> LOC=AE26;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<5> IOSTANDARD=LVCMOS18;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<5> PULLDOWN;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<5> SLEW=SLOW;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<5> DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<6> LOC=AC25;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<6> IOSTANDARD=LVCMOS18;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<6> PULLDOWN;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<6> SLEW=SLOW;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<6> DRIVE=2;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<7> LOC=AC24;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<7> IOSTANDARD=LVCMOS18;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<7> PULLDOWN;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<7> SLEW=SLOW;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<7> DRIVE=2;

#### Module IIC_EEPROM constraints

Net fpga_0_IIC_EEPROM_Scl_pin LOC=F9;
Net fpga_0_IIC_EEPROM_Scl_pin SLEW = SLOW;
Net fpga_0_IIC_EEPROM_Scl_pin DRIVE = 6;
Net fpga_0_IIC_EEPROM_Scl_pin IOSTANDARD=LVCMOS33;
Net fpga_0_IIC_EEPROM_Sda_pin LOC=F8;
Net fpga_0_IIC_EEPROM_Sda_pin SLEW = SLOW;
Net fpga_0_IIC_EEPROM_Sda_pin DRIVE = 6;
Net fpga_0_IIC_EEPROM_Sda_pin IOSTANDARD=LVCMOS33;

#### Module SRAM constraints