system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AB10;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AB11;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AC11;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=Y8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AA10;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=Y7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AA7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=Y6;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AD6;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AD5;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AD4;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AA8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AB7;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AD3;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AB4;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AA4;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AC8;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AD10;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=W4;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin TIG;

#### Module DDR_SDRAM constraints

Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=C18;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=C17;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=E17;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=D16;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=C16;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=B15;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=B16;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=A15;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=F17;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=C21;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=D18;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=D21;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=E20;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=E13;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=C14;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=B17;
Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=J24;
Net fpga_0_DDR_SDRAM_DDR_CE_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=H23;
Net fpga_0_DDR_SDRAM_DDR_CS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=A17;
Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=D20;
Net fpga_0_DDR_SDRAM_DDR_WE_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=K20;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=C23;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> LOC=D23;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> LOC=E22;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQS<0> LOC=L23;
Net fpga_0_DDR_SDRAM_DDR_DQS<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQS<1> LOC=D24;
Net fpga_0_DDR_SDRAM_DDR_DQS<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQS<2> LOC=C24;
Net fpga_0_DDR_SDRAM_DDR_DQS<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQS<3> LOC=K22;
Net fpga_0_DDR_SDRAM_DDR_DQS<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<0> LOC=F23;
Net fpga_0_DDR_SDRAM_DDR_DQ<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<1> LOC=E21;
Net fpga_0_DDR_SDRAM_DDR_DQ<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<2> LOC=F20;
Net fpga_0_DDR_SDRAM_DDR_DQ<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<3> LOC=G20;
Net fpga_0_DDR_SDRAM_DDR_DQ<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<4> LOC=F19;
Net fpga_0_DDR_SDRAM_DDR_DQ<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<5> LOC=G19;
Net fpga_0_DDR_SDRAM_DDR_DQ<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<6> LOC=H19;
Net fpga_0_DDR_SDRAM_DDR_DQ<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<7> LOC=C19;
Net fpga_0_DDR_SDRAM_DDR_DQ<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<8> LOC=E23;
Net fpga_0_DDR_SDRAM_DDR_DQ<8> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<9> LOC=G24;
Net fpga_0_DDR_SDRAM_DDR_DQ<9> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<10> LOC=F24;
Net fpga_0_DDR_SDRAM_DDR_DQ<10> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<11> LOC=H22;
Net fpga_0_DDR_SDRAM_DDR_DQ<11> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<12> LOC=M24;
Net fpga_0_DDR_SDRAM_DDR_DQ<12> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<13> LOC=K23;
Net fpga_0_DDR_SDRAM_DDR_DQ<13> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<14> LOC=N24;
Net fpga_0_DDR_SDRAM_DDR_DQ<14> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<15> LOC=L24;
Net fpga_0_DDR_SDRAM_DDR_DQ<15> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<16> LOC=F18;
Net fpga_0_DDR_SDRAM_DDR_DQ<16> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<17> LOC=N23;
Net fpga_0_DDR_SDRAM_DDR_DQ<17> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<18> LOC=J23;
Net fpga_0_DDR_SDRAM_DDR_DQ<18> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<19> LOC=N22;
Net fpga_0_DDR_SDRAM_DDR_DQ<19> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<20> LOC=H24;
Net fpga_0_DDR_SDRAM_DDR_DQ<20> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<21> LOC=L19;
Net fpga_0_DDR_SDRAM_DDR_DQ<21> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<22> LOC=G22;
Net fpga_0_DDR_SDRAM_DDR_DQ<22> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<23> LOC=F22;
Net fpga_0_DDR_SDRAM_DDR_DQ<23> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<24> LOC=J19;
Net fpga_0_DDR_SDRAM_DDR_DQ<24> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<25> LOC=L18;
Net fpga_0_DDR_SDRAM_DDR_DQ<25> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<26> LOC=M22;
Net fpga_0_DDR_SDRAM_DDR_DQ<26> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<27> LOC=D19;
Net fpga_0_DDR_SDRAM_DDR_DQ<27> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<28> LOC=K18;
Net fpga_0_DDR_SDRAM_DDR_DQ<28> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<29> LOC=G21;
Net fpga_0_DDR_SDRAM_DDR_DQ<29> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<30> LOC=J21;
Net fpga_0_DDR_SDRAM_DDR_DQ<30> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_DQ<31> LOC=K21;
Net fpga_0_DDR_SDRAM_DDR_DQ<31> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=C13;
Net fpga_0_DDR_SDRAM_DDR_Clk_pin IOSTANDARD = DIFF_SSTL2_II;
Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=C12;
Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin IOSTANDARD = DIFF_SSTL2_II;