system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC=AB14;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin LOC=M5;
Net sys_rst_pin PULLUP;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;
NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP";
NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP";
NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP";
TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS  TIG;

## IO Devices constraints

#### Display controller

Net plb_npi_vga_controller_0_tft_lcd_hsync_pin LOC=C3;
Net plb_npi_vga_controller_0_tft_lcd_vsync_pin LOC=D4;
# Net plb_npi_vga_controller_0_tft_lcd_r_pin<1>  LOC=F3;
Net plb_npi_vga_controller_0_tft_lcd_r_pin<2>  LOC=H7;
Net plb_npi_vga_controller_0_tft_lcd_r_pin<3>  LOC=E3;
Net plb_npi_vga_controller_0_tft_lcd_r_pin<4>  LOC=G5;
Net plb_npi_vga_controller_0_tft_lcd_r_pin<5>  LOC=D3;
# Net plb_npi_vga_controller_0_tft_lcd_g_pin<1>  LOC=J3;
Net plb_npi_vga_controller_0_tft_lcd_g_pin<2>  LOC=K7;
Net plb_npi_vga_controller_0_tft_lcd_g_pin<3>  LOC=K3;
Net plb_npi_vga_controller_0_tft_lcd_g_pin<4>  LOC=G10;
Net plb_npi_vga_controller_0_tft_lcd_g_pin<5>  LOC=K6;
# Net plb_npi_vga_controller_0_tft_lcd_b_pin<1>  LOC=F4;
Net plb_npi_vga_controller_0_tft_lcd_b_pin<2>  LOC=J4;
Net plb_npi_vga_controller_0_tft_lcd_b_pin<3>  LOC=G9;
Net plb_npi_vga_controller_0_tft_lcd_b_pin<4>  LOC=J5;
Net plb_npi_vga_controller_0_tft_lcd_b_pin<5>  LOC=H3;

Net vga_clk_pin LOC=AC7;
Net vga_clk_pin IOSTANDARD=LVCMOS33;

#### PS/2 controller

Net plb_ps2_controller_0_mouse_clk_pin  LOC=E15;
Net plb_ps2_controller_0_mouse_data_pin LOC=D14;
Net plb_ps2_controller_0_key_clk_pin    LOC=E11;
Net plb_ps2_controller_0_key_data_pin   LOC=K10;

#### Module RS232_Uart constraints

Net fpga_0_RS232_Uart_RX_pin LOC=T4;
Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_Uart_TX_pin LOC=T8;
Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;

#### Module LEDs_4Bit constraints

Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=A10;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=B10;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=F13;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=F14;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;
Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;

#### Module LEDs_Positions constraints

Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=E6;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=G12;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=L9;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=L7;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=G4;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;

#### Module Push_Buttons_Position constraints

Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> LOC=D6;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> PULLDOWN;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> SLEW = SLOW;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> DRIVE = 2;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<0> TIG;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> LOC=K8;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> PULLDOWN;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> SLEW = SLOW;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> DRIVE = 2;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<1> TIG;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> LOC=L10;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> PULLDOWN;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> SLEW = SLOW;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> DRIVE = 2;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<2> TIG;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> LOC=M6;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> PULLDOWN;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> SLEW = SLOW;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> DRIVE = 2;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<3> TIG;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> LOC=G11;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> PULLDOWN;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> SLEW = SLOW;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> DRIVE = 2;
Net fpga_0_Push_Buttons_Position_GPIO_IO_pin<4> TIG;

#### Module SysACE_CompactFlash constraints

Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AE13;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AC9;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AD8;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AD9;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AB6;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AA3;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=Y3;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AD11;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33;