system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

AREA_GROUP "cal_ctl" RANGE = SLICE_X28Y70:SLICE_X39Y83;
AREA_GROUP "cal_ctl" GROUP = CLOSED;


##############################################################################
# IOB and AREA constraints
##############################################################################

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/datapath_iobs/gen_dqs[*].dqs_iob*"    IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/datapath_iobs/gen_dq[*].dq_iob*"      IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_addr[*].addr_iob" IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_ba[*].ba_iob"     IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_cke[*].cke_iob"   IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/ras_iob"              IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/cas_iob"              IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/we_iob"               IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dqs_div/dqs_rst_iob"                       IOB = TRUE;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[1]*u_fifo_bit"   LOC = SLICE_X2Y36;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[1]*u_fifo_bit" LOC = SLICE_X2Y37;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[0]*u_fifo_bit"   LOC = SLICE_X0Y36;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[0]*u_fifo_bit" LOC = SLICE_X0Y37;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[2]*u_fifo_bit"   LOC = SLICE_X2Y32;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y33;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[3]*u_fifo_bit"   LOC = SLICE_X0Y32;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y33;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[5]*u_fifo_bit"   LOC = SLICE_X2Y24;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[5]*u_fifo_bit" LOC = SLICE_X2Y25;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[4]*u_fifo_bit"   LOC = SLICE_X0Y24;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[4]*u_fifo_bit" LOC = SLICE_X0Y25;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[7]*u_fifo_bit"   LOC = SLICE_X0Y20;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y21;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[6]*u_fifo_bit"   LOC = SLICE_X2Y20;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y21;



INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[1]*u_fifo_bit"   LOC = SLICE_X0Y82;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[1]*u_fifo_bit" LOC = SLICE_X0Y83;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[0]*u_fifo_bit"   LOC = SLICE_X2Y82;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[0]*u_fifo_bit" LOC = SLICE_X2Y83;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[3]*u_fifo_bit"   LOC = SLICE_X0Y76;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y77;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[2]*u_fifo_bit"   LOC = SLICE_X2Y76;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y77;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[5]*u_fifo_bit"   LOC = SLICE_X0Y68;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[5]*u_fifo_bit" LOC = SLICE_X0Y69;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[4]*u_fifo_bit"   LOC = SLICE_X2Y68;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[4]*u_fifo_bit" LOC = SLICE_X2Y69;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[7]*u_fifo_bit"   LOC = SLICE_X0Y64;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y65;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[6]*u_fifo_bit"   LOC = SLICE_X2Y64;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y65;




#############################################################
## DQS 0 Col 0
#############################################################
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.one"   LOC = SLICE_X2Y29;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.one"   BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.two"   LOC = SLICE_X2Y29;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.two"   BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.three" LOC = SLICE_X2Y28;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.three" BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.four"  LOC = SLICE_X2Y28;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.four"  BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.five"  LOC = SLICE_X3Y29;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.five"  BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.six"   LOC = SLICE_X3Y28;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.six"   BEL = G;

#############################################################
## DQS 0 Col 1
#############################################################

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.one"   LOC = SLICE_X0Y29;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.one"   BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.two"   LOC = SLICE_X0Y29;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.two"   BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.three" LOC = SLICE_X0Y28;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.three" BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.four"  LOC = SLICE_X0Y28;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.four"  BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.five"  LOC = SLICE_X1Y29;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.five"  BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.six"   LOC = SLICE_X1Y28;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.six"   BEL = G;

#############################################################
## DQS 1 Col 0
#############################################################
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.one"   LOC = SLICE_X2Y73;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.one"   BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.two"   LOC = SLICE_X2Y73;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.two"   BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.three" LOC = SLICE_X2Y72;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.three" BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.four"  LOC = SLICE_X2Y72;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.four"  BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.five"  LOC = SLICE_X3Y73;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.five"  BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.six"   LOC = SLICE_X3Y72;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.six"   BEL = G;

#############################################################
## DQS 1 Col 1
#############################################################

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.one"   LOC = SLICE_X0Y73;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.one"   BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.two"   LOC = SLICE_X0Y73;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.two"   BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.three" LOC = SLICE_X0Y72;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.three" BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.four"  LOC = SLICE_X0Y72;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.four"  BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.five"  LOC = SLICE_X1Y73;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.five"  BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.six"   LOC = SLICE_X1Y72;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.six"   BEL = G;

#############################################################
## WR ADDR 0
#############################################################
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X1Y30;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X1Y30;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X1Y31;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X1Y31;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X3Y30;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X3Y30;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X3Y31;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X3Y31;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/*" LOC = SLICE_X1Y33;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/*" LOC = SLICE_X3Y33;

#############################################################
## WR ADDR 1
#############################################################
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X1Y74;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X1Y74;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X1Y75;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X1Y75;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X3Y74;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X3Y74;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X3Y75;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X3Y75;

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/*" LOC = SLICE_X1Y77;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/*" LOC = SLICE_X3Y77;

#############################################################
## DQS Loopback
#############################################################
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.one"   LOC = SLICE_X0Y9;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.one"   BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.two"   LOC = SLICE_X0Y8;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.two"   BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.three" LOC = SLICE_X0Y9;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.three" BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.four"  LOC = SLICE_X1Y8;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.four"  BEL = F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.five"  LOC = SLICE_X1Y8;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.five"  BEL = G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.six"   LOC = SLICE_X1Y9;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.six"   BEL = G;