system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=R2;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=P1;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=F4;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=H4;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=H3;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=H1;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=H2;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=N4;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=T2;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=N5;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=P2;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=K5;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=K6;
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=C2;
Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=K3;
Net fpga_0_DDR_SDRAM_DDR_CE_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=K4;
Net fpga_0_DDR_SDRAM_DDR_CS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=C1;
Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=D1;
Net fpga_0_DDR_SDRAM_DDR_WE_n_pin IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=J2;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=J1;
Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQS<0> LOC=L6;
Net fpga_0_DDR_SDRAM_DDR_DQS<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQS<1> LOC=G3;
Net fpga_0_DDR_SDRAM_DDR_DQS<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQS<1> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<0> LOC=L2;
Net fpga_0_DDR_SDRAM_DDR_DQ<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<0> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<1> LOC=L1;
Net fpga_0_DDR_SDRAM_DDR_DQ<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<1> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<2> LOC=L3;
Net fpga_0_DDR_SDRAM_DDR_DQ<2> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<2> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<3> LOC=L4;
Net fpga_0_DDR_SDRAM_DDR_DQ<3> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<3> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<4> LOC=M3;
Net fpga_0_DDR_SDRAM_DDR_DQ<4> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<4> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<5> LOC=M4;
Net fpga_0_DDR_SDRAM_DDR_DQ<5> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<5> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<6> LOC=M5;
Net fpga_0_DDR_SDRAM_DDR_DQ<6> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<6> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<7> LOC=M6;
Net fpga_0_DDR_SDRAM_DDR_DQ<7> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<7> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<8> LOC=E2;
Net fpga_0_DDR_SDRAM_DDR_DQ<8> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<8> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<9> LOC=E1;
Net fpga_0_DDR_SDRAM_DDR_DQ<9> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<9> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<10> LOC=F1;
Net fpga_0_DDR_SDRAM_DDR_DQ<10> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<10> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<11> LOC=F2;
Net fpga_0_DDR_SDRAM_DDR_DQ<11> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<11> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<12> LOC=G6;
Net fpga_0_DDR_SDRAM_DDR_DQ<12> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<12> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<13> LOC=G5;
Net fpga_0_DDR_SDRAM_DDR_DQ<13> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<13> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<14> LOC=H6;
Net fpga_0_DDR_SDRAM_DDR_DQ<14> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<14> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQ<15> LOC=H5;
Net fpga_0_DDR_SDRAM_DDR_DQ<15> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_DQ<15> PULLUP;
Net fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O LOC=P13;
Net fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O IOSTANDARD = LVCMOS33;
Net fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O LOC=P13;
Net fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O IOSTANDARD = LVCMOS33;


############################################################################
# Placement constraints for luts in tap delay ckt 
############################################################################

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0"  RLOC=X0Y6;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0"  U_SET = "tap_dly0_u_set";
 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" RLOC=X0Y6;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1"  U_SET = "tap_dly0_u_set";
 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" RLOC=X0Y7;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" RLOC=X0Y7;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" RLOC=X1Y6;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" RLOC=X1Y6;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" RLOC=X1Y7;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" RLOC=X1Y7;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7"  U_SET = "tap_dly0_u_set";
  
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" RLOC=X0Y4;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8"  U_SET = "tap_dly0_u_set";
 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" RLOC=X0Y4;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9"  U_SET = "tap_dly0_u_set";
 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" RLOC=X0Y5;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10"  U_SET = "tap_dly0_u_set";
 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" RLOC=X0Y5;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11"  U_SET = "tap_dly0_u_set";
 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" RLOC=X1Y4;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12"  U_SET = "tap_dly0_u_set";
 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" RLOC=X1Y4;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13"  U_SET = "tap_dly0_u_set";
 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" RLOC=X1Y5;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" RLOC=X1Y5;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" RLOC=X0Y2;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" RLOC=X0Y2;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" RLOC=X0Y3;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" RLOC=X0Y3;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" RLOC=X1Y2;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" RLOC=X1Y2;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" RLOC=X1Y3;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" RLOC=X1Y3;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" RLOC=X0Y0;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" RLOC=X0Y0;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" RLOC=X0Y1;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26"  U_SET = "tap_dly0_u_set";

INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" RLOC=X0Y1;
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27"  U_SET = "tap_dly0_u_set";