system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC=c9;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin LOC=K17;
Net sys_rst_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin PULLDOWN;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
Net sys_rst_pin TIG;

## IO Devices constraints

#### PS/2 Mouse and Keyboard

# Primary connection
NET "plb_ps2_controller_0_mouse_clk_pin" LOC = "G14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "plb_ps2_controller_0_mouse_data_pin" LOC = "G13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
# Secondary connection (requires additional connector on FX2)
NET "plb_ps2_controller_0_key_clk_pin" LOC = "A6" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "plb_ps2_controller_0_key_clk_pin" PULLUP;
NET "plb_ps2_controller_0_key_data_pin" LOC = "B6" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "plb_ps2_controller_0_key_data_pin" PULLUP;

#### VGA CONNECTOR

Net tft_lcd_hsync LOC = C14 | IOSTANDARD = LVCMOS33;
Net tft_lcd_vsync LOC = A16 | IOSTANDARD = LVCMOS33;
Net tft_lcd_r<2> LOC = B14 | IOSTANDARD = LVCMOS33;
Net tft_lcd_r<3> LOC = B13 | IOSTANDARD = LVCMOS33;
Net tft_lcd_r<4> LOC = A14	| IOSTANDARD = LVCMOS33;
Net tft_lcd_r<5> LOC = A13	| IOSTANDARD = LVCMOS33;
Net tft_lcd_g<2> LOC = A11 | IOSTANDARD = LVCMOS33;
Net tft_lcd_g<3> LOC = C4  | IOSTANDARD = LVCMOS33;
Net tft_lcd_g<4> LOC = B16	| IOSTANDARD = LVCMOS33;
Net tft_lcd_g<5> LOC = D14	| IOSTANDARD = LVCMOS33;
Net tft_lcd_b<2> LOC = A8	| IOSTANDARD = LVCMOS33;
Net tft_lcd_b<3> LOC = B11	| IOSTANDARD = LVCMOS33;
Net tft_lcd_b<4> LOC = E13	| IOSTANDARD = LVCMOS33;
Net tft_lcd_b<5> LOC = G9	| IOSTANDARD = LVCMOS33;

# ON BOARD VGA CONNECTOR

Net vga_hsync  LOC = F15 | IOSTANDARD = LVCMOS33;
Net vga_vsync  LOC = F14 | IOSTANDARD = LVCMOS33;
Net vga_r      LOC = H14 | IOSTANDARD = LVCMOS33;
Net vga_g      LOC = H15 | IOSTANDARD = LVCMOS33;
Net vga_b      LOC = G15 | IOSTANDARD = LVCMOS33;

#### Module RS232_DTE constraints

Net fpga_0_RS232_DTE_RX_pin LOC=U8;
Net fpga_0_RS232_DTE_RX_pin IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_DTE_TX_pin LOC=M13;
Net fpga_0_RS232_DTE_TX_pin IOSTANDARD = LVCMOS33;

#### Module LEDs_8Bit constraints

Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0> LOC=F9;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1> LOC=E9;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2> LOC=D11;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3> LOC=C11;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4> LOC=F11;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5> LOC=E11;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6> LOC=E12;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7> LOC=F12;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7> IOSTANDARD = LVCMOS33;

#### Module DIP_Switches_4Bit constraints

Net fpga_0_DIP_Switches_4Bit_GPIO_in_pin<0> LOC=N17 | PULLDOWN;
Net fpga_0_DIP_Switches_4Bit_GPIO_in_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_DIP_Switches_4Bit_GPIO_in_pin<1> LOC=H18 | PULLDOWN;
Net fpga_0_DIP_Switches_4Bit_GPIO_in_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_DIP_Switches_4Bit_GPIO_in_pin<2> LOC=L14 | PULLDOWN;
Net fpga_0_DIP_Switches_4Bit_GPIO_in_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_DIP_Switches_4Bit_GPIO_in_pin<3> LOC=L13 | PULLDOWN;
Net fpga_0_DIP_Switches_4Bit_GPIO_in_pin<3> IOSTANDARD = LVCMOS33;

#### Module Buttons_4Bit constraints

Net fpga_0_Buttons_4Bit_GPIO_in_pin<0> LOC=D18 | PULLDOWN;
Net fpga_0_Buttons_4Bit_GPIO_in_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_Buttons_4Bit_GPIO_in_pin<1> LOC=H13 | PULLDOWN;
Net fpga_0_Buttons_4Bit_GPIO_in_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_Buttons_4Bit_GPIO_in_pin<2> LOC=V4 | PULLDOWN;
Net fpga_0_Buttons_4Bit_GPIO_in_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_Buttons_4Bit_GPIO_in_pin<3> LOC=V16 | PULLDOWN;
Net fpga_0_Buttons_4Bit_GPIO_in_pin<3> IOSTANDARD = LVCMOS33;

#### Module FLASH constraints

Net fpga_0_FLASH_Mem_A_pin<31> LOC=h17;
Net fpga_0_FLASH_Mem_A_pin<31> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<30> LOC=j13;
Net fpga_0_FLASH_Mem_A_pin<30> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<29> LOC=j12;
Net fpga_0_FLASH_Mem_A_pin<29> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<28> LOC=j14;
Net fpga_0_FLASH_Mem_A_pin<28> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<27> LOC=j15;
Net fpga_0_FLASH_Mem_A_pin<27> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<26> LOC=j16;
Net fpga_0_FLASH_Mem_A_pin<26> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<25> LOC=j17;
Net fpga_0_FLASH_Mem_A_pin<25> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<24> LOC=k14;
Net fpga_0_FLASH_Mem_A_pin<24> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<23> LOC=k15;
Net fpga_0_FLASH_Mem_A_pin<23> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<22> LOC=k12;
Net fpga_0_FLASH_Mem_A_pin<22> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<21> LOC=k13;
Net fpga_0_FLASH_Mem_A_pin<21> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<20> LOC=l15;
Net fpga_0_FLASH_Mem_A_pin<20> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<19> LOC=l16;
Net fpga_0_FLASH_Mem_A_pin<19> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<18> LOC=t18;
Net fpga_0_FLASH_Mem_A_pin<18> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<17> LOC=r18;
Net fpga_0_FLASH_Mem_A_pin<17> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<16> LOC=t17;
Net fpga_0_FLASH_Mem_A_pin<16> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<15> LOC=u18;
Net fpga_0_FLASH_Mem_A_pin<15> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<14> LOC=t16;
Net fpga_0_FLASH_Mem_A_pin<14> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<13> LOC=u15;
Net fpga_0_FLASH_Mem_A_pin<13> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<12> LOC=v15;
Net fpga_0_FLASH_Mem_A_pin<12> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<11> LOC=t12;
Net fpga_0_FLASH_Mem_A_pin<11> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<10> LOC=v13;
Net fpga_0_FLASH_Mem_A_pin<10> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<9> LOC=v12;
Net fpga_0_FLASH_Mem_A_pin<9> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<8> LOC=n11;
Net fpga_0_FLASH_Mem_A_pin<8> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<7> LOC=n10;
Net fpga_0_FLASH_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<6> LOC=p10;
Net fpga_0_FLASH_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<5> LOC=r10;
Net fpga_0_FLASH_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<4> LOC=v9;
Net fpga_0_FLASH_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<3> LOC=u9;
Net fpga_0_FLASH_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<2> LOC=r9;
Net fpga_0_FLASH_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<1> LOC=m9;
Net fpga_0_FLASH_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<0> LOC=n9;
Net fpga_0_FLASH_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_OEN_pin LOC=c18;
Net fpga_0_FLASH_Mem_OEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_WEN_pin LOC=d17;
Net fpga_0_FLASH_Mem_WEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_CEN_pin<0> LOC=d16;
Net fpga_0_FLASH_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_emc_ben_gnd_pin LOC=c17;
Net fpga_0_FLASH_emc_ben_gnd_pin IOSTANDARD = LVCMOS33;

#### Module DDR_SDRAM constraints

Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=J5;
Net fpga_0_DDR_SDRAM_DDR_Clk_pin IOSTANDARD = DIFF_SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=J4;
Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin IOSTANDARD = DIFF_SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=T1;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=R3;