system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29" RLOC=X1Y0;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30" RLOC=X1Y1;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31" RLOC=X1Y1;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

##############################################################################
# Placement constraints for first stage flops in tapped delay circuit
##############################################################################

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r0"    RLOC=X0Y6;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r0"   U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r1" RLOC=X0Y6;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r1"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r2" RLOC=X0Y7;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r2"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r3" RLOC=X0Y7;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r3"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r4" RLOC=X1Y6;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r4"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r5" RLOC=X1Y6;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r5"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r6" RLOC=X1Y7;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r6"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r7" RLOC=X1Y7;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r7"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r8" RLOC=X0Y4;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r8"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r9" RLOC=X0Y4;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r9"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r10" RLOC=X0Y5;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r10"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r11" RLOC=X0Y5;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r11"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r12" RLOC=X1Y4;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r12"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r13" RLOC=X1Y4;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r13"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r14" RLOC=X1Y5;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r14"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r15" RLOC=X1Y5;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r15"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r16" RLOC=X0Y2;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r16"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r17" RLOC=X0Y2;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r17"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r18" RLOC=X0Y3;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r18"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r19" RLOC=X0Y3;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r19"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r20" RLOC=X1Y2;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r20"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r21" RLOC=X1Y2;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r21"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r22" RLOC=X1Y3;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r22"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r23" RLOC=X1Y3;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r23"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r24" RLOC=X0Y0;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r24"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r25" RLOC=X0Y0;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r25"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r26" RLOC=X0Y1;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r26"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r27" RLOC=X0Y1;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r27"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r28" RLOC=X1Y0;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r28"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r29" RLOC=X1Y0;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r29"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r30" RLOC=X1Y1;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r30"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r31" RLOC=X1Y1;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.r31"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

##############################################################################
# BEL constraints for luts in tapped delay circuit
##############################################################################

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" BEL= F;  
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29" BEL= F;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30" BEL= G;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31" BEL= F;

##############################################################################
# IOB and AREA constraints
##############################################################################

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/datapath_iobs/gen_dqs[*].dqs_iob*" 		IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/datapath_iobs/gen_dq[*].dq_iob*" 		IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_addr[*].addr_iob" 		IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_ba[*].ba_iob"		IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_cke[*].cke_iob"		IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/ras_iob"  			IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/cas_iob"  			IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/we_iob"   			IOB = TRUE;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dqs_div/dqs_rst_iob" 				IOB = TRUE;


INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/cal_ctl/*" AREA_GROUP = cal_ctl;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/*" AREA_GROUP = cal_ctl;
AREA_GROUP "cal_ctl" RANGE = SLICE_X4Y52:SLICE_X15Y65;
AREA_GROUP "cal_ctl" GROUP = CLOSED;

##############################################################################
# Delay constraints
##############################################################################

# This constraints are here to help the tools place this logic to strive for these delay constraints.
# They may not get met, but the net delay should be in a range of <400 - 600 ps>
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[7]"				MAXDELAY = 410ps;
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[15]"				MAXDELAY = 400ps;
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[23]"      				MAXDELAY = 400ps;

# This constraint may not get met, but this helps the tools achieve an optimal placement.  The range should be <400 - 600 ps>
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dqs_int_delay_in*"                       				MAXDELAY = 550ps;

# This constraint may not get met, but this helps the tools achieve an optimal placement.  The range should be <200 - 360 ps>
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[*]*u_dqs_delay_col*/delay*" 	MAXDELAY = 190ps;
#NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/dqs_delayed_col*<*>"          				MAXDELAY = 1000ps;

# This constraints are here to help the tools place this logic to strive for these delay constraints. They may not get met
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/rst_dqs_div"            		MAXDELAY = 3000ps;
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path*rst_dqs_div_delayed*"   	           	                MAXDELAY = 3000ps;