system.ucf

Genode FX is a composition of hardware and software components that enable the creation of fully fl

Net fpga_0_DDR2_SDRAM_DDR2_DQ<15> IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin LOC=H4;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin LOC=H3;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin IOSTANDARD = SSTL18_II;

#### Module FLASH constraints

Net fpga_0_FLASH_Mem_A_pin<10> LOC=C21;
Net fpga_0_FLASH_Mem_A_pin<10> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<11> LOC=C22;
Net fpga_0_FLASH_Mem_A_pin<11> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<12> LOC=F21;
Net fpga_0_FLASH_Mem_A_pin<12> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<13> LOC=F22;
Net fpga_0_FLASH_Mem_A_pin<13> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<14> LOC=H20;
Net fpga_0_FLASH_Mem_A_pin<14> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<15> LOC=H21;
Net fpga_0_FLASH_Mem_A_pin<15> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<16> LOC=G22;
Net fpga_0_FLASH_Mem_A_pin<16> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<17> LOC=H22;
Net fpga_0_FLASH_Mem_A_pin<17> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<18> LOC=J20;
Net fpga_0_FLASH_Mem_A_pin<18> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<19> LOC=J21;
Net fpga_0_FLASH_Mem_A_pin<19> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<20> LOC=J22;
Net fpga_0_FLASH_Mem_A_pin<20> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<21> LOC=K22;
Net fpga_0_FLASH_Mem_A_pin<21> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<22> LOC=N17;
Net fpga_0_FLASH_Mem_A_pin<22> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<23> LOC=N18;
Net fpga_0_FLASH_Mem_A_pin<23> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<24> LOC=N19;
Net fpga_0_FLASH_Mem_A_pin<24> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<25> LOC=N20;
Net fpga_0_FLASH_Mem_A_pin<25> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<26> LOC=N21;
Net fpga_0_FLASH_Mem_A_pin<26> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<27> LOC=N22;
Net fpga_0_FLASH_Mem_A_pin<27> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<28> LOC=P18;
Net fpga_0_FLASH_Mem_A_pin<28> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<29> LOC=R19;
Net fpga_0_FLASH_Mem_A_pin<29> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_A_pin<30> LOC=T18;
Net fpga_0_FLASH_Mem_A_pin<30> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<0> LOC=T17;
Net fpga_0_FLASH_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<1> LOC=R21;
Net fpga_0_FLASH_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<2> LOC=T22;
Net fpga_0_FLASH_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<3> LOC=U22;
Net fpga_0_FLASH_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<4> LOC=U21;
Net fpga_0_FLASH_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<5> LOC=V22;
Net fpga_0_FLASH_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<6> LOC=W22;
Net fpga_0_FLASH_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<7> LOC=T20;
Net fpga_0_FLASH_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<8> LOC=Y9;
Net fpga_0_FLASH_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<9> LOC=AB9;
Net fpga_0_FLASH_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<10> LOC=Y11;
Net fpga_0_FLASH_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<11> LOC=AB11;
Net fpga_0_FLASH_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<12> LOC=U13;
Net fpga_0_FLASH_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<13> LOC=AA17;
Net fpga_0_FLASH_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<14> LOC=Y17;
Net fpga_0_FLASH_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_DQ_pin<15> LOC=AB20;
Net fpga_0_FLASH_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_OEN_pin LOC=W19;
Net fpga_0_FLASH_Mem_OEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_WEN_pin LOC=AA22;
Net fpga_0_FLASH_Mem_WEN_pin IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_Mem_CEN_pin<0> LOC=W20;
Net fpga_0_FLASH_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_emc_ben_gnd_pin LOC=Y21;
Net fpga_0_FLASH_emc_ben_gnd_pin IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_emc_rp_pin LOC=R22;
Net fpga_0_FLASH_emc_rp_pin IOSTANDARD = LVCMOS33;
Net fpga_0_FLASH_emc_wp_pin LOC=E14;
Net fpga_0_FLASH_emc_wp_pin IOSTANDARD = LVCMOS33;



##############################################################################
# Placement constraints for LUTs in tapped delay circuit
##############################################################################

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0"  RLOC=X0Y6;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";
 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" RLOC=X0Y6;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";
 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" RLOC=X0Y7;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" RLOC=X0Y7;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" RLOC=X1Y6;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" RLOC=X1Y6;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" RLOC=X1Y7;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" RLOC=X1Y7;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";
  
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" RLOC=X0Y4;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";
 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" RLOC=X0Y4;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" RLOC=X0Y5;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";
 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" RLOC=X0Y5;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";
 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" RLOC=X1Y4;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";
 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" RLOC=X1Y4;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";
 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" RLOC=X1Y5;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" RLOC=X1Y5;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" RLOC=X0Y2;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" RLOC=X0Y2;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" RLOC=X0Y3;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" RLOC=X0Y3;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" RLOC=X1Y2;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" RLOC=X1Y2;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" RLOC=X1Y3;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" RLOC=X1Y3;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" RLOC=X0Y0;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" RLOC=X0Y0;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" RLOC=X0Y1;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" RLOC=X0Y1;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";

INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28" RLOC=X1Y0;
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28"  U_SET = "*/mpmc_core_0.gen_s3_ddr*/mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0";